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sysmobts: configure AEMIF CS3 for the FPGA 

Signed-off-by: Jan Luebbe <jluebbe@debian.org>
This commit is contained in:
Jan Luebbe 2015-11-22 14:41:51 +01:00 committed by Holger Hans Peter Freyther
parent cf239b47f8
commit d85cee4420
1 changed files with 21 additions and 0 deletions
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21
arch/arm/boards/sysmobts/board.c
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@ -180,8 +180,29 @@ static int sysmobts_coredevices_init(void)
coredevice_initcall(sysmobts_coredevices_init);
#define DAVINCI_PLLM (0x01C40910) /* PLL 1 Multiplier */
#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */
#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
static int sysmobts_devices_init(void)
{
/* Configure AEMIF AWCCR */
writel(DAVINCI_AWCCR_VAL, DAVINCI_AWCCR);
/* DM644X @ 594/297 MHz */
if ( (readl(DAVINCI_PLLM) & 0x0FF) < 22 ) {
/* Configure AEMIF CS3 (fpga) */
writel(DAVINCI_A2CR_VAL, DAVINCI_A2CR);
/* DM644X @ 810/405 MHz */
} else {
/* Configure AEMIF CS3 (fpga) */
writel(DAVINCI_A2CR_VAL8, DAVINCI_A2CR);
}
sysmobts_set_ethaddr();
platform_device_register(&dm644x_emac_device);