mci: bcm2835: use the registered device clkdev
Switch from local mailbox code to using the newly created clock device. Signed-off-by: Andre Heider <a.heider@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -28,13 +28,14 @@
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* Author: Wilhelm Lundgren <wilhelm.lundgren@cybercom.com>
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*/
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#include <asm/mmu.h>
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#include <common.h>
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#include <init.h>
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#include <mci.h>
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#include <io.h>
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#include <malloc.h>
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#include <clock.h>
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#include <linux/clk.h>
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#include "mci-bcm2835.h"
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#include "sdhci.h"
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@ -469,53 +470,6 @@ int bcm2835_mci_reset(struct mci_host *mci, struct device_d *mci_dev)
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return bcm2835_mci_wait_command_done(host);
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}
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static u32 bcm2835_mci_get_emmc_clock(struct msg_get_clock_rate *clk_data)
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{
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u32 val;
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struct bcm2835_mbox_regs __iomem *regs =
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(struct bcm2835_mbox_regs *) BCM2835_MBOX_PHYSADDR;
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/*Read out old msg*/
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while (true) {
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val = readl(®s->status);
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if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
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break;
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val = readl(®s->read);
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}
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/*Check for ok to write*/
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while (true) {
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val = readl(®s->status);
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if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
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break;
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}
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val = BCM2835_MBOX_PROP_CHAN + ((u32) &clk_data->hdr);
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dma_flush_range((u32)clk_data, (u32)clk_data + sizeof(*clk_data));
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writel(val, ®s->write);
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while (true) {
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/* Wait for the response */
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while (true) {
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val = readl(®s->status);
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if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
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break;
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}
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/* Read the response */
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val = readl(®s->read);
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if ((val & 0x0F) == BCM2835_MBOX_PROP_CHAN)
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break;
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}
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dma_inv_range((u32)clk_data, (u32)clk_data + sizeof(*clk_data));
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if ((val & ~0x0F) == ((u32) &clk_data->hdr))
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if (clk_data->get_clock_rate.tag_hdr.val_len
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& BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)
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return 1;
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return 0;
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}
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static int bcm2835_mci_detect(struct device_d *dev)
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{
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struct bcm2835_mci_host *host = dev->priv;
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@ -526,7 +480,22 @@ static int bcm2835_mci_detect(struct device_d *dev)
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static int bcm2835_mci_probe(struct device_d *hw_dev)
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{
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struct bcm2835_mci_host *host;
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struct msg_get_clock_rate *clk_data;
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static struct clk *clk;
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int ret;
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clk = clk_get(hw_dev, NULL);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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dev_err(hw_dev, "clock not found: %d\n", ret);
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return ret;
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}
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ret = clk_enable(clk);
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if (ret) {
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dev_err(hw_dev, "clock failed to enable: %d\n", ret);
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clk_put(clk);
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return ret;
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}
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host = xzalloc(sizeof(*host));
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host->mci.send_cmd = bcm2835_mci_request;
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@ -534,31 +503,7 @@ static int bcm2835_mci_probe(struct device_d *hw_dev)
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host->mci.init = bcm2835_mci_reset;
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host->mci.hw_dev = hw_dev;
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host->hw_dev = hw_dev;
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/* Allocate a buffer thats 16 bytes aligned in memory
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* Of the 32 bits address passed into the mbox 28 bits
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* are the address of the buffer, lower 4 bits is channel
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*/
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clk_data = memalign(16, sizeof(struct msg_get_clock_rate));
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memset(clk_data, 0, sizeof(struct msg_get_clock_rate));
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clk_data->hdr.buf_size = sizeof(struct msg_get_clock_rate);
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clk_data->get_clock_rate.tag_hdr.tag = BCM2835_MBOX_TAG_GET_CLOCK_RATE;
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clk_data->get_clock_rate.tag_hdr.val_buf_size =
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sizeof(clk_data->get_clock_rate.body);
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clk_data->get_clock_rate.tag_hdr.val_len =
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sizeof(clk_data->get_clock_rate.body.req);
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clk_data->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
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if (!bcm2835_mci_get_emmc_clock(clk_data)) {
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dev_warn(host->hw_dev,
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"Failed getting emmc clock, lets go anyway with 50MHz\n");
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host->max_clock = 50000000;
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} else {
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host->max_clock = clk_data->get_clock_rate.body.resp.rate_hz;
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dev_info(host->hw_dev, "Got emmc clock at %d Hz\n",
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host->max_clock);
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}
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host->max_clock = clk_get_rate(clk);
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host->regs = dev_request_mem_region(hw_dev, 0);
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if (host->regs == NULL) {
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dev_err(host->hw_dev, "Failed request mem region, aborting...\n");
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@ -23,51 +23,3 @@
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#define MAX_CLK_DIVIDER_V3 2046
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#define MAX_CLK_DIVIDER_V2 256
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/*this is only for mbox comms*/
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#define BCM2835_MBOX_PHYSADDR 0x2000b880
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#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
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#define BCM2835_MBOX_CLOCK_ID_EMMC 1
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#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
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#define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
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#define BCM2835_MBOX_PROP_CHAN 8
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#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
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struct bcm2835_mbox_regs {
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u32 read;
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u32 rsvd0[5];
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u32 status;
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u32 config;
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u32 write;
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};
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struct bcm2835_mbox_hdr {
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u32 buf_size;
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u32 code;
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};
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struct bcm2835_mbox_tag_hdr {
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u32 tag;
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u32 val_buf_size;
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u32 val_len;
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};
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struct bcm2835_mbox_tag_get_clock_rate {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 clock_id;
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} req;
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struct {
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u32 clock_id;
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u32 rate_hz;
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} resp;
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} body;
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};
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struct msg_get_clock_rate {
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struct bcm2835_mbox_hdr hdr;
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struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
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u32 end_tag;
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};
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