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sama5d3x: fix AT91_SMC_CS offset stride 

As stated in section 29.19.32 of SAMA5D3 Series datasheet, to move
from CS(n) to CS(n+1) the stride is 0x14 and not 0x10 as in the
other AT91 CPUs

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Matteo Fortini 2014-05-29 14:44:39 +02:00 committed by Sascha Hauer
parent d4d9fc125f
commit dc2dacd261
1 changed files with 3 additions and 1 deletions
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4
arch/arm/mach-at91/sam9_smc.c
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@ -12,11 +12,13 @@
#include <init.h>
#include <io.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x14 : 0x10)
#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * AT91_SMC_CS_STRIDE))
static void __iomem *smc_base_addr[2];