net smc911x: add support for external PHY
On LAN9115/LAN9117/LAN9215/LAN9217, external PHYs are supported. Switch to external PHY based on hardware strap pin and/or override flags. Also add a mask to platform data selecting external PHY address to be used. Code based on linux/drivers/net/ethernet/smsc/smsc911x.c (fd9abb3d, d23f028a). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -44,6 +44,10 @@ struct smc911x_priv {
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int shift;
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int shift;
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int generation;
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int generation;
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unsigned int flags;
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unsigned int idrev;
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unsigned int using_extphy;
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unsigned int phy_mask;
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u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
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u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
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void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
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void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
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@ -225,6 +229,60 @@ static int smc911x_phy_write(struct mii_bus *bus, int phy_addr,
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return 0;
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return 0;
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}
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}
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/* Switch to external phy. Assumes tx and rx are stopped. */
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static void smsc911x_phy_enable_external(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 hwcfg = smc911x_reg_read(priv, HW_CFG);
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/* Disable phy clocks to the MAC */
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hwcfg &= (~HW_CFG_PHY_CLK_SEL);
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hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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udelay(10); /* Enough time for clocks to stop */
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/* Switch to external phy */
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hwcfg |= HW_CFG_EXT_PHY_EN;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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/* Enable phy clocks to the MAC */
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hwcfg &= (~HW_CFG_PHY_CLK_SEL);
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hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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udelay(10); /* Enough time for clocks to restart */
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/* Switch MDIO/MDC to external PHY */
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hwcfg |= HW_CFG_SMI_SEL;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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}
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/* Autodetects and enables external phy if present on supported chips.
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* autodetection can be overridden by specifying SMC911X_FORCE_INTERNAL_PHY
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* or SMC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
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static void smsc911x_phy_initialise_external(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 hwcfg = smc911x_reg_read(priv, HW_CFG);
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if (priv->flags & SMC911X_FORCE_INTERNAL_PHY) {
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dev_info(edev->parent, "Forcing internal PHY\n");
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priv->using_extphy = 0;
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} else if (priv->flags & SMC911X_FORCE_EXTERNAL_PHY) {
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dev_info(edev->parent, "Forcing external PHY\n");
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smsc911x_phy_enable_external(edev);
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priv->using_extphy = 1;
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} else if (hwcfg & HW_CFG_EXT_PHY_DET) {
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dev_info(edev->parent,
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"HW_CFG EXT_PHY_DET set, using external PHY\n");
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smsc911x_phy_enable_external(edev);
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priv->using_extphy = 1;
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} else {
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dev_info(edev->parent,
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"HW_CFG EXT_PHY_DET clear, using internal PHY\n");
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priv->using_extphy = 0;
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}
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}
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static int smc911x_phy_reset(struct eth_device *edev)
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static int smc911x_phy_reset(struct eth_device *edev)
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{
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{
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struct smc911x_priv *priv = edev->priv;
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struct smc911x_priv *priv = edev->priv;
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@ -284,14 +342,41 @@ static void smc911x_reset(struct eth_device *edev)
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/* Set to LED outputs */
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/* Set to LED outputs */
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smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
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smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
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/* Select internal/external PHY */
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switch (priv->idrev & 0xFFFF0000) {
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case 0x01170000:
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case 0x01150000:
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case 0x117A0000:
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case 0x115A0000:
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/* External PHY supported, try to autodetect */
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smsc911x_phy_initialise_external(edev);
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break;
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default:
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dev_dbg(edev->parent, "External PHY is not supported, "
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"using internal PHY\n");
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priv->using_extphy = 0;
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break;
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}
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if (!priv->using_extphy) {
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/* Mask all PHYs except ID 1 (internal) */
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priv->miibus.phy_mask = ~(1 << 1);
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} else {
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/* Mask PHYs as requested (or try all if mask is 0) */
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/* Attn.: first probed PHY is used by phy_device_connect */
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priv->miibus.phy_mask = priv->phy_mask;
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}
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}
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}
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static void smc911x_enable(struct eth_device *edev)
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static void smc911x_enable(struct eth_device *edev)
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{
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{
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struct smc911x_priv *priv = edev->priv;
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struct smc911x_priv *priv = edev->priv;
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u32 hw_cfg_phy_settings;
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/* Enable TX */
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/* Enable TX */
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smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF);
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hw_cfg_phy_settings = smc911x_reg_read(priv, HW_CFG) & (HW_CFG_PHY_CLK_SEL|HW_CFG_SMI_SEL|HW_CFG_EXT_PHY_EN);
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smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF | hw_cfg_phy_settings);
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smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
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smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
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@ -306,7 +391,8 @@ static int smc911x_eth_open(struct eth_device *edev)
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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int ret;
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int ret;
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ret = phy_device_connect(edev, &priv->miibus, 1, NULL,
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/* use first probed PHY (see also phy_mask) */
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ret = phy_device_connect(edev, &priv->miibus, -1, NULL,
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0, PHY_INTERFACE_MODE_NA);
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0, PHY_INTERFACE_MODE_NA);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -426,8 +512,11 @@ static int smc911x_probe(struct device_d *dev)
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is_32bit = is_32bit == IORESOURCE_MEM_32BIT;
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is_32bit = is_32bit == IORESOURCE_MEM_32BIT;
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priv->base = dev_request_mem_region(dev, 0);
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priv->base = dev_request_mem_region(dev, 0);
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if (pdata && pdata->shift)
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if (pdata) {
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priv->shift = pdata->shift;
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priv->shift = pdata->shift;
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priv->flags = pdata->flags;
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priv->phy_mask = pdata->phy_mask;
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}
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if (is_32bit) {
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if (is_32bit) {
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if (priv->shift) {
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if (priv->shift) {
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@ -483,7 +572,7 @@ static int smc911x_probe(struct device_d *dev)
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return -ENODEV;
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return -ENODEV;
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}
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}
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val = smc911x_reg_read(priv, ID_REV);
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priv->idrev = val = smc911x_reg_read(priv, ID_REV);
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switch (val & 0xFFFF0000) {
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switch (val & 0xFFFF0000) {
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case 0x01180000:
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case 0x01180000:
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case 0x01170000:
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case 0x01170000:
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@ -13,6 +13,12 @@
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*/
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*/
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struct smc911x_plat {
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struct smc911x_plat {
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int shift;
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int shift;
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unsigned int flags;
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unsigned int phy_mask; /* external PHY only: mask out PHYs,
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e.g. ~(1 << 5) to use PHY addr 5 */
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};
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};
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#define SMC911X_FORCE_INTERNAL_PHY 0x01
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#define SMC911X_FORCE_EXTERNAL_PHY 0x02
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#endif /* __SMC911X_PLATFORM_H_ */
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#endif /* __SMC911X_PLATFORM_H_ */
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