ppc: gianfar MDIO buses
This commit creates MDIO bus devices to separate the MDIO bus abstraction from the Ethernet device initialisation. It also updates the configuration of the P2020RDB ports. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
0cbb215519
commit
eb99c09f7c
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@ -59,12 +59,19 @@
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#define SYSCLK_50 50000000
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#define SYSCLK_100 100000000
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/* Ethernet. Use eTSEC3 */
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/* Define attributes for eTSEC2 and eTSEC3 */
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static struct gfar_info_struct gfar_info[] = {
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{
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.phyaddr = 0,
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.tbiana = 0x1a0,
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.tbicr = 0x9140,
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.mdiobus_tbi = 1,
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},
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{
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.phyaddr = 1,
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.tbiana = 0,
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.tbicr = 0,
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.mdiobus_tbi = 2,
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},
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};
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@ -82,8 +89,8 @@ static int devices_init(void)
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add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
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0x100, IORESOURCE_MEM, &i2cplat);
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/* eTSEC3 */
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fsl_eth_init(3, &gfar_info[0]);
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fsl_eth_init(2, &gfar_info[0]);
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fsl_eth_init(3, &gfar_info[1]);
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devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
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"self0");
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@ -22,28 +22,40 @@
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <mach/immap_85xx.h>
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#include <mach/gianfar.h>
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int fsl_eth_init(int num, struct gfar_info_struct *gf)
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static int fsl_phy_init(void)
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{
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struct resource *res;
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int i;
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void __iomem *base = IOMEM(GFAR_BASE_ADDR + GFAR_TBIPA_OFFSET);
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res = xzalloc(3 * sizeof(struct resource));
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/* TSEC interface registers */
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res[0].start = GFAR_BASE_ADDR + ((num - 1) * 0x1000);
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res[0].end = res[0].start + 0x1000 - 1;
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res[0].flags = IORESOURCE_MEM;
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/* External PHY access always through eTSEC1 */
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res[1].start = MDIO_BASE_ADDR;
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res[1].end = res[1].start + 0x1000 - 1;
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res[1].flags = IORESOURCE_MEM;
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/* Access to TBI/RTBI interface. */
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res[2].start = MDIO_BASE_ADDR + ((num - 1) * 0x1000);
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res[2].end = res[2].start + 0x1000 - 1;
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res[2].flags = IORESOURCE_MEM;
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add_generic_device_res("gfar", DEVICE_ID_DYNAMIC, res, 3, gf);
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/*
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* The TBI address must be initialised to enable the PHY to
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* link up after the MDIO reset.
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*/
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out_be32(base, GFAR_TBIPA_END);
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/* All ports access external PHYs via the "gfar-mdio" device */
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add_generic_device("gfar-mdio", 0, NULL, MDIO_BASE_ADDR,
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0x1000, IORESOURCE_MEM, NULL);
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for (i = 1; i < 3; i++) {
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out_be32(base + (i * 0x1000), GFAR_TBIPA_END - i);
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/* Use "gfar-tbiphy" devices to access internal PHY. */
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add_generic_device("gfar-tbiphy", i, NULL,
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MDIO_BASE_ADDR + (i * 0x1000),
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0x1000, IORESOURCE_MEM, NULL);
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}
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return 0;
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}
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coredevice_initcall(fsl_phy_init);
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int fsl_eth_init(int num, struct gfar_info_struct *gf)
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{
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add_generic_device("gfar", DEVICE_ID_DYNAMIC, NULL,
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GFAR_BASE_ADDR + ((num - 1) * 0x1000), 0x1000,
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IORESOURCE_MEM, gf);
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return 0;
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}
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@ -22,10 +22,14 @@
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* Platform data for the Motorola Triple Speed Ethernet Controller
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*/
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#define GFAR_TBIPA_OFFSET 0x030 /* TBI PHY address */
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#define GFAR_TBIPA_END 0x1f /* Last valid PHY address */
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struct gfar_info_struct {
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unsigned int phyaddr;
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unsigned int tbiana;
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unsigned int tbicr;
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unsigned int mdiobus_tbi;
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};
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int fsl_eth_init(int num, struct gfar_info_struct *gf);
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@ -184,10 +184,11 @@ static int gfar_open(struct eth_device *edev)
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{
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int ix;
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struct gfar_private *priv = edev->priv;
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struct gfar_phy *phy = priv->gfar_mdio;
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void __iomem *regs = priv->regs;
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int ret;
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ret = phy_device_connect(edev, &priv->miibus, priv->phyaddr,
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ret = phy_device_connect(edev, &phy->miibus, priv->phyaddr,
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gfar_adjust_link, 0, PHY_INTERFACE_MODE_NA);
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if (ret)
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return ret;
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@ -305,44 +306,51 @@ static uint gfar_local_mdio_read(void __iomem *phyregs, uint phyid, uint regnum)
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static void gfar_configure_serdes(struct gfar_private *priv)
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{
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gfar_local_mdio_write(priv->phyregs_sgmii,
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struct gfar_phy *phy = priv->gfar_tbi;
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gfar_local_mdio_write(phy->regs,
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in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_ANA,
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priv->tbiana);
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gfar_local_mdio_write(priv->phyregs_sgmii,
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gfar_local_mdio_write(phy->regs,
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in_be32(priv->regs + GFAR_TBIPA_OFFSET),
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GFAR_TBI_TBICON, GFAR_TBICON_CLK_SELECT);
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gfar_local_mdio_write(priv->phyregs_sgmii,
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gfar_local_mdio_write(phy->regs,
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in_be32(priv->regs + GFAR_TBIPA_OFFSET), GFAR_TBI_CR,
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priv->tbicr);
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}
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/* Reset the internal and external PHYs. */
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static void gfar_init_phy(struct eth_device *dev)
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static int gfar_bus_reset(struct mii_bus *bus)
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{
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struct gfar_private *priv = dev->priv;
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void __iomem *regs = priv->regs;
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struct gfar_phy *phy = bus->priv;
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uint64_t start;
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/* Assign a Physical address to the TBI */
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out_be32(regs + GFAR_TBIPA_OFFSET, GFAR_TBIPA_VALUE);
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/* Reset MII (due to new addresses) */
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out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
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out_be32(priv->phyregs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
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out_be32(phy->regs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_RESET);
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out_be32(phy->regs + GFAR_MIIMCFG_OFFSET, GFAR_MIIMCFG_INIT_VALUE);
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start = get_time_ns();
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while (!is_timeout(start, 10 * MSECOND)) {
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if (!(in_be32(priv->phyregs + GFAR_MIIMMIND_OFFSET) &
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if (!(in_be32(phy->regs + GFAR_MIIMMIND_OFFSET) &
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GFAR_MIIMIND_BUSY))
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break;
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}
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return 0;
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}
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gfar_local_mdio_write(priv->phyregs, priv->phyaddr, GFAR_MIIM_CR,
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/* Reset the external PHYs. */
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static void gfar_init_phy(struct eth_device *dev)
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{
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struct gfar_private *priv = dev->priv;
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struct gfar_phy *phy = priv->gfar_mdio;
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void __iomem *regs = priv->regs;
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uint64_t start;
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gfar_local_mdio_write(phy->regs, priv->phyaddr, GFAR_MIIM_CR,
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GFAR_MIIM_CR_RST);
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start = get_time_ns();
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while (!is_timeout(start, 10 * MSECOND)) {
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if (!(gfar_local_mdio_read(priv->phyregs, priv->phyaddr,
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if (!(gfar_local_mdio_read(phy->regs, priv->phyaddr,
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GFAR_MIIM_CR) & GFAR_MIIM_CR_RST))
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break;
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}
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@ -433,13 +441,12 @@ static int gfar_recv(struct eth_device *edev)
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/* Read a MII PHY register. */
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static int gfar_miiphy_read(struct mii_bus *bus, int addr, int reg)
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{
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struct device_d *dev = bus->parent;
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struct gfar_private *priv = bus->priv;
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struct gfar_phy *phy = bus->priv;
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int ret;
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ret = gfar_local_mdio_read(priv->phyregs, addr, reg);
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ret = gfar_local_mdio_read(phy->regs, addr, reg);
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if (ret == -EIO)
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dev_err(dev, "Can't read PHY at address %d\n", addr);
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dev_err(phy->dev, "Can't read PHY at address %d\n", addr);
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return ret;
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}
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@ -448,15 +455,14 @@ static int gfar_miiphy_read(struct mii_bus *bus, int addr, int reg)
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static int gfar_miiphy_write(struct mii_bus *bus, int addr, int reg,
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u16 value)
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{
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struct device_d *dev = bus->parent;
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struct gfar_private *priv = bus->priv;
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struct gfar_phy *phy = bus->priv;
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unsigned short val = value;
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int ret;
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ret = gfar_local_mdio_write(priv->phyregs, addr, reg, val);
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ret = gfar_local_mdio_write(phy->regs, addr, reg, val);
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if (ret)
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dev_err(dev, "Can't write PHY at address %d\n", addr);
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dev_err(phy->dev, "Can't write PHY at address %d\n", addr);
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return 0;
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}
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@ -470,7 +476,9 @@ static int gfar_probe(struct device_d *dev)
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struct gfar_info_struct *gfar_info = dev->platform_data;
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struct eth_device *edev;
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struct gfar_private *priv;
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struct device_d *mdev;
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size_t size;
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char devname[16];
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char *p;
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priv = xzalloc(sizeof(struct gfar_private));
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@ -480,14 +488,28 @@ static int gfar_probe(struct device_d *dev)
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edev = &priv->edev;
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priv->regs = dev_request_mem_region(dev, 0);
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priv->phyregs = dev_request_mem_region(dev, 1);
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priv->phyregs_sgmii = dev_request_mem_region(dev, 2);
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priv->mdiobus_tbi = gfar_info->mdiobus_tbi;
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priv->regs = dev_get_mem_region(dev, 0);
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priv->phyaddr = gfar_info->phyaddr;
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priv->tbicr = gfar_info->tbicr;
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priv->tbiana = gfar_info->tbiana;
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mdev = get_device_by_name("gfar-mdio0");
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if (mdev == NULL) {
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pr_err("gfar-mdio0 was not found\n");
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return -ENODEV;
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}
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priv->gfar_mdio = mdev->priv;
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if (priv->mdiobus_tbi != 0) {
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sprintf(devname, "%s%d", "gfar-tbiphy", priv->mdiobus_tbi);
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mdev = get_device_by_name(devname);
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if (mdev == NULL) {
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pr_err("%s was not found\n", devname);
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return -ENODEV;
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}
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}
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priv->gfar_tbi = mdev->priv;
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/*
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* Allocate descriptors 64-bit aligned. Descriptors
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* are 8 bytes in size.
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@ -512,15 +534,8 @@ static int gfar_probe(struct device_d *dev)
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udelay(2);
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clrbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
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priv->miibus.read = gfar_miiphy_read;
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priv->miibus.write = gfar_miiphy_write;
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priv->miibus.priv = priv;
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priv->miibus.parent = dev;
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gfar_init_phy(edev);
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mdiobus_register(&priv->miibus);
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return eth_register(edev);
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}
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@ -529,3 +544,64 @@ static struct driver_d gfar_eth_driver = {
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.probe = gfar_probe,
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};
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device_platform_driver(gfar_eth_driver);
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static int gfar_phy_probe(struct device_d *dev)
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{
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struct gfar_phy *phy;
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int ret;
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phy = xzalloc(sizeof(*phy));
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phy->dev = dev;
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phy->regs = dev_get_mem_region(dev, 0);
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if (!phy->regs)
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return -ENOMEM;
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phy->miibus.read = gfar_miiphy_read;
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phy->miibus.write = gfar_miiphy_write;
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phy->miibus.priv = phy;
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phy->miibus.reset = gfar_bus_reset;
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phy->miibus.parent = dev;
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dev->priv = phy;
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ret = mdiobus_register(&phy->miibus);
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if (ret)
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return ret;
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return 0;
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}
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static struct driver_d gfar_phy_driver = {
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.name = "gfar-mdio",
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.probe = gfar_phy_probe,
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};
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register_driver_macro(coredevice, platform, gfar_phy_driver);
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static int gfar_tbiphy_probe(struct device_d *dev)
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{
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struct gfar_phy *phy;
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int ret;
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phy = xzalloc(sizeof(*phy));
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phy->dev = dev;
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phy->regs = dev_get_mem_region(dev, 0);
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if (!phy->regs)
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return -ENOMEM;
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phy->miibus.read = gfar_miiphy_read;
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phy->miibus.write = gfar_miiphy_write;
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phy->miibus.priv = phy;
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phy->miibus.parent = dev;
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dev->priv = phy;
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ret = mdiobus_register(&phy->miibus);
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if (ret)
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return ret;
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return 0;
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}
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static struct driver_d gfar_tbiphy_driver = {
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.name = "gfar-tbiphy",
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.probe = gfar_tbiphy_probe,
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};
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register_driver_macro(coredevice, platform, gfar_tbiphy_driver);
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@ -205,7 +205,6 @@ struct rxbd8 {
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#define GFAR_ECNTRL_OFFSET 0x020 /* Ethernet Control */
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#define GFAR_MINFLR_OFFSET 0x024 /* Minimum Frame Length */
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#define GFAR_DMACTRL_OFFSET 0x02c /* DMA Control */
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#define GFAR_TBIPA_OFFSET 0x030 /* TBI PHY address */
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/* eTSEC transmit control and status register */
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#define GFAR_TSTAT_OFFSET 0x104 /* transmit status register */
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@ -263,13 +262,19 @@ struct rxbd8 {
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#define GFAR_ATTR_OFFSET 0xbf8 /* Default Attribute Register */
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#define GFAR_ATTRELI_OFFSET 0xbfc /* Default Attribute Extract Len/Idx */
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struct gfar_phy {
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void __iomem *regs;
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struct device_d *dev;
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struct mii_bus miibus;
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};
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struct gfar_private {
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struct eth_device edev;
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void __iomem *regs;
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void __iomem *phyregs;
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void __iomem *phyregs_sgmii;
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int mdiobus_tbi;
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struct gfar_phy *gfar_mdio;
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struct gfar_phy *gfar_tbi;
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struct phy_info *phyinfo;
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struct mii_bus miibus;
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volatile struct txbd8 *txbd;
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volatile struct rxbd8 *rxbd;
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uint txidx;
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