pci: Add i.MX6 pcie support
Based on the corresponding kernel driver with changes to make it work on barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7e2b903274
commit
f929fab29c
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@ -174,6 +174,7 @@ config ARCH_IMX6
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select CPU_V7
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select PINCTRL_IMX_IOMUX_V3
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select COMMON_CLK_OF_PROVIDER
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select HW_HAS_PCI
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config ARCH_IMX6SX
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bool
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@ -40,6 +40,13 @@ config PCI_TEGRA
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select OF_PCI
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select PCI
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config PCI_IMX6
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bool "Freescale i.MX6 PCIe controller"
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depends on ARCH_IMX6
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select PCIE_DW
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select OF_PCI
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select PCI
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endmenu
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endif
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@ -10,3 +10,4 @@ CPPFLAGS += $(ccflags-y)
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o pci-mvebu-phy.o
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obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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@ -0,0 +1,612 @@
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/*
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* PCIe host controller driver for Freescale i.MX6 SoCs
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*
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* Copyright (C) 2013 Kosagi
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* http://www.kosagi.com
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*
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* Author: Sean Cross <xobs@kosagi.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <clock.h>
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#include <malloc.h>
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#include <io.h>
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#include <init.h>
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#include <gpio.h>
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#include <asm/mmu.h>
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#include <of_gpio.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <of_address.h>
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#include <of_pci.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <mfd/imx6q-iomuxc-gpr.h>
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#include <mach/imx6-regs.h>
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#include "pcie-designware.h"
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#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
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struct imx6_pcie {
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int reset_gpio;
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struct clk *pcie_bus;
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struct clk *pcie_phy;
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struct clk *pcie;
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struct pcie_port pp;
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void __iomem *iomuxc_gpr;
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void __iomem *mem_base;
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};
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/* PCIe Root Complex registers (memory-mapped) */
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#define PCIE_RC_LCR 0x7c
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
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#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
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#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
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#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
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#define PCIE_PHY_CTRL_WR_LOC 18
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#define PCIE_PHY_CTRL_RD_LOC 19
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
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static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
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{
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u32 val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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val = readl(dbi_base + PCIE_PHY_STAT);
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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wait_counter++;
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if (val == exp_val)
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return 0;
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udelay(1);
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} while (wait_counter < max_iterations);
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return -ETIMEDOUT;
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}
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static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
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{
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u32 val;
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int ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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writel(val, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
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{
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u32 val, phy_ctl;
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int ret;
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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/* assert Read signal */
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phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
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writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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val = readl(dbi_base + PCIE_PHY_STAT);
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*data = val & 0xffff;
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/* deassert Read signal */
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writel(0x00, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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return 0;
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}
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static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
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{
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u32 var;
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int ret;
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/* write addr */
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/* cap addr */
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ret = pcie_phy_wait_ack(dbi_base, addr);
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if (ret)
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return ret;
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* capture data */
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var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
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writel(var, dbi_base + PCIE_PHY_CTRL);
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert cap data */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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/* assert wr signal */
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var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack */
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ret = pcie_phy_poll_ack(dbi_base, 1);
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if (ret)
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return ret;
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/* deassert wr signal */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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writel(var, dbi_base + PCIE_PHY_CTRL);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(dbi_base, 0);
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if (ret)
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return ret;
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writel(0x0, dbi_base + PCIE_PHY_CTRL);
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return 0;
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}
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static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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u32 val, gpr1, gpr12;
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/*
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* If the bootloader already enabled the link we need some special
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* handling to get the core back into a state where it is safe to
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* touch it for configuration. As there is no dedicated reset signal
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* wired up for MX6QDL, we need to manually force LTSSM into "detect"
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* state before completely disabling LTSSM, which is a prerequisite
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* for core configuration.
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*
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* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
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* indication that the bootloader activated the link.
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*/
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gpr1 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
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(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
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val = readl(pp->dbi_base + PCIE_PL_PFLR);
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val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
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val |= PCIE_PL_PFLR_FORCE_LINK;
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writel(val, pp->dbi_base + PCIE_PL_PFLR);
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gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2;
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writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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}
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gpr1 |= IMX6Q_GPR1_PCIE_TEST_PD;
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writel(gpr1, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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gpr1 &= ~IMX6Q_GPR1_PCIE_REF_CLK_EN;
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writel(gpr1, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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return 0;
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}
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static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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int ret;
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u32 gpr1;
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ret = clk_enable(imx6_pcie->pcie_phy);
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if (ret)
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goto err_pcie_phy;
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ret = clk_enable(imx6_pcie->pcie_bus);
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if (ret)
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goto err_pcie_bus;
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ret = clk_enable(imx6_pcie->pcie);
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if (ret)
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goto err_pcie;
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/* power up core phy and enable ref clock */
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gpr1 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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gpr1 &= ~IMX6Q_GPR1_PCIE_TEST_PD;
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writel(gpr1, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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/*
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* the async reset input need ref clock to sync internally,
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* when the ref clock comes after reset, internal synced
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* reset time is too short, cannot meet the requirement.
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* add one ~10us delay here.
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*/
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udelay(10);
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gpr1 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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gpr1 |= IMX6Q_GPR1_PCIE_REF_CLK_EN;
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writel(gpr1, imx6_pcie->iomuxc_gpr + IOMUXC_GPR1);
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/* allow the clocks to stabilize */
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udelay(200);
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/* Some boards don't have PCIe reset GPIO. */
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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mdelay(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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}
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return 0;
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err_pcie:
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clk_disable(imx6_pcie->pcie_bus);
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err_pcie_bus:
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clk_disable(imx6_pcie->pcie_phy);
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err_pcie_phy:
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return ret;
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}
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static void imx6_pcie_init_phy(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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u32 gpr12, gpr8;
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gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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gpr12 &= ~IMX6Q_GPR12_PCIE_CTL_2;
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writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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/* configure constant input signal to the pcie ctrl and phy */
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gpr12 &= ~IMX6Q_GPR12_DEVICE_TYPE;
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gpr12 |= PCI_EXP_TYPE_ROOT_PORT << 12;
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writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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gpr12 &= ~IMX6Q_GPR12_LOS_LEVEL;
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gpr12 |= 9 << 4;
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writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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gpr8 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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gpr8 &= ~IMX6Q_GPR8_TX_DEEMPH_GEN1;
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writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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gpr8 &= ~IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB;
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writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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gpr8 &= ~IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB;
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gpr8 |= 20 << 12;
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writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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gpr8 &= ~IMX6Q_GPR8_TX_SWING_FULL;
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gpr8 |= 127 << 18;
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writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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gpr8 &= ~IMX6Q_GPR8_TX_SWING_LOW;
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gpr8 |= 127 << 25;
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writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
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}
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static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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{
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uint64_t start = get_time_ns();
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while (1) {
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if (dw_pcie_link_up(pp))
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return 0;
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if (!is_timeout(start, SECOND))
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continue;
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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}
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static int imx6_pcie_start_link(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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uint32_t tmp;
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int ret;
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u32 gpr12;
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u64 start;
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/*
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* Force Gen1 operation when starting the link. In case the link is
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* started in Gen2 mode, there is a possibility the devices on the
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* bus will not be detected at all. This happens with PCIe switches.
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*/
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tmp = readl(pp->dbi_base + PCIE_RC_LCR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
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writel(tmp, pp->dbi_base + PCIE_RC_LCR);
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/* Start LTSSM. */
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gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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gpr12 |= IMX6Q_GPR12_PCIE_CTL_2;
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writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
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ret = imx6_pcie_wait_for_link(pp);
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if (ret)
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return ret;
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/* Allow Gen2 mode after the link is up. */
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tmp = readl(pp->dbi_base + PCIE_RC_LCR);
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
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writel(tmp, pp->dbi_base + PCIE_RC_LCR);
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/*
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* Start Directed Speed Change so the best possible speed both link
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* partners support can be negotiated.
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*/
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tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp |= PORT_LOGIC_SPEED_CHANGE;
|
||||
writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
|
||||
start = get_time_ns();
|
||||
while (!is_timeout(start, SECOND)) {
|
||||
tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
/* Test if the speed change finished. */
|
||||
if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
|
||||
break;
|
||||
}
|
||||
|
||||
/* Make sure link training is finished as well! */
|
||||
if (tmp & PORT_LOGIC_SPEED_CHANGE)
|
||||
ret = -EINVAL;
|
||||
else
|
||||
ret = imx6_pcie_wait_for_link(pp);
|
||||
|
||||
if (ret) {
|
||||
dev_err(pp->dev, "Failed to bring link up!\n");
|
||||
} else {
|
||||
tmp = readl(pp->dbi_base + 0x80);
|
||||
dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void imx6_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
imx6_pcie_assert_core_reset(pp);
|
||||
|
||||
imx6_pcie_init_phy(pp);
|
||||
|
||||
imx6_pcie_deassert_core_reset(pp);
|
||||
|
||||
dw_pcie_setup_rc(pp);
|
||||
|
||||
imx6_pcie_start_link(pp);
|
||||
}
|
||||
|
||||
static void imx6_pcie_reset_phy(struct pcie_port *pp)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
|
||||
temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
|
||||
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
|
||||
pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
|
||||
|
||||
udelay(2000);
|
||||
|
||||
pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
|
||||
temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
|
||||
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
|
||||
pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
|
||||
}
|
||||
|
||||
static int imx6_pcie_link_up(struct pcie_port *pp)
|
||||
{
|
||||
u32 rc, debug_r0, rx_valid;
|
||||
int count = 5;
|
||||
|
||||
/*
|
||||
* Test if the PHY reports that the link is up and also that the LTSSM
|
||||
* training finished. There are three possible states of the link when
|
||||
* this code is called:
|
||||
* 1) The link is DOWN (unlikely)
|
||||
* The link didn't come up yet for some reason. This usually means
|
||||
* we have a real problem somewhere. Reset the PHY and exit. This
|
||||
* state calls for inspection of the DEBUG registers.
|
||||
* 2) The link is UP, but still in LTSSM training
|
||||
* Wait for the training to finish, which should take a very short
|
||||
* time. If the training does not finish, we have a problem and we
|
||||
* need to inspect the DEBUG registers. If the training does finish,
|
||||
* the link is up and operating correctly.
|
||||
* 3) The link is UP and no longer in LTSSM training
|
||||
* The link is up and operating correctly.
|
||||
*/
|
||||
while (1) {
|
||||
rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
|
||||
if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
|
||||
break;
|
||||
if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
|
||||
return 1;
|
||||
if (!count--)
|
||||
break;
|
||||
dev_dbg(pp->dev, "Link is up, but still in training\n");
|
||||
/*
|
||||
* Wait a little bit, then re-check if the link finished
|
||||
* the training.
|
||||
*/
|
||||
udelay(1000);
|
||||
}
|
||||
/*
|
||||
* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
|
||||
* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
|
||||
* If (MAC/LTSSM.state == Recovery.RcvrLock)
|
||||
* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
|
||||
* to gen2 is stuck
|
||||
*/
|
||||
pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
|
||||
debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
|
||||
|
||||
if (rx_valid & 0x01)
|
||||
return 0;
|
||||
|
||||
if ((debug_r0 & 0x3f) != 0x0d)
|
||||
return 0;
|
||||
|
||||
dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
|
||||
dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
|
||||
|
||||
imx6_pcie_reset_phy(pp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pcie_host_ops imx6_pcie_host_ops = {
|
||||
.link_up = imx6_pcie_link_up,
|
||||
.host_init = imx6_pcie_host_init,
|
||||
};
|
||||
|
||||
static int __init imx6_add_pcie_port(struct pcie_port *pp,
|
||||
struct device_d *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &imx6_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to initialize host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init imx6_pcie_probe(struct device_d *dev)
|
||||
{
|
||||
struct imx6_pcie *imx6_pcie;
|
||||
struct pcie_port *pp;
|
||||
struct device_node *np = dev->device_node;
|
||||
int ret;
|
||||
|
||||
imx6_pcie = xzalloc(sizeof(*imx6_pcie));
|
||||
if (!imx6_pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
pp = &imx6_pcie->pp;
|
||||
pp->dev = dev;
|
||||
|
||||
pp->dbi_base = dev_request_mem_region(dev, 0);
|
||||
if (IS_ERR(pp->dbi_base))
|
||||
return PTR_ERR(pp->dbi_base);
|
||||
|
||||
/* Fetch GPIOs */
|
||||
imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
|
||||
if (gpio_is_valid(imx6_pcie->reset_gpio)) {
|
||||
ret = gpio_request_one(imx6_pcie->reset_gpio,
|
||||
GPIOF_OUT_INIT_LOW, "PCIe reset");
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to get reset gpio\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fetch clocks */
|
||||
imx6_pcie->pcie_phy = clk_get(dev, "pcie_phy");
|
||||
if (IS_ERR(imx6_pcie->pcie_phy)) {
|
||||
dev_err(dev, "pcie_phy clock source missing or invalid\n");
|
||||
return PTR_ERR(imx6_pcie->pcie_phy);
|
||||
}
|
||||
|
||||
imx6_pcie->pcie_bus = clk_get(dev, "pcie_bus");
|
||||
if (IS_ERR(imx6_pcie->pcie_bus)) {
|
||||
dev_err(dev, "pcie_bus clock source missing or invalid\n");
|
||||
return PTR_ERR(imx6_pcie->pcie_bus);
|
||||
}
|
||||
|
||||
imx6_pcie->pcie = clk_get(dev, "pcie");
|
||||
if (IS_ERR(imx6_pcie->pcie)) {
|
||||
dev_err(dev, "pcie clock source missing or invalid\n");
|
||||
return PTR_ERR(imx6_pcie->pcie);
|
||||
}
|
||||
|
||||
/* Grab GPR config register range */
|
||||
imx6_pcie->iomuxc_gpr = IOMEM(MX6_IOMUXC_BASE_ADDR);
|
||||
|
||||
ret = imx6_add_pcie_port(pp, dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id imx6_pcie_of_match[] = {
|
||||
{ .compatible = "fsl,imx6q-pcie", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct driver_d imx6_pcie_driver = {
|
||||
.name = "imx6-pcie",
|
||||
.of_compatible = DRV_OF_COMPAT(imx6_pcie_of_match),
|
||||
.probe = imx6_pcie_probe,
|
||||
};
|
||||
device_platform_driver(imx6_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
|
||||
MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -259,6 +259,12 @@
|
|||
#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24)
|
||||
#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28)
|
||||
|
||||
#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
|
||||
#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
|
||||
#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
|
||||
|
||||
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
|
||||
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
|
||||
|
||||
|
|
@ -291,7 +297,9 @@
|
|||
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
|
||||
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
|
||||
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
|
||||
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
|
||||
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
|
||||
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
|
||||
|
||||
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
|
||||
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
|
||||
|
|
|
|||
Loading…
Reference in New Issue