The relocation code can now relocate from anywhere to
the RAM.
The old code assumed that the binary was copied to the RAM
by some PBL and then it just relocated the .text section
from the loaded address to the linked address.
Now, it first checks if vectors are somewhere else than the
linked address. If yes, there are copied to address 0 (or
to the exception vector base address if register EVBAR is
present).
Then, the .text section is relocated from its current location
to the RAM.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can compile barebox for multiple boards at once, but currently
they all share a single default environment. This patch adds a
defaultenv_append() which boards can call to customize the default
environment during runtime. Each board now generate default environment
snippets using bbenv-y and add them during runtime with defaultenv_append()
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
OpenRISC is the original flagship project of the OpenCores community.
This project aims to develop a series of general purpose open source
RISC CPU architectures.
A team from OpenCores provided the first implementation, the OpenRISC
1200, written in the Verilog hardware description language.
Even though I should have created an mach-or1200 directory, it is not
necessary for now. The OpenRISC 1200 CPU is the only one available and
it will be for some time.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Franck Jullien
Sascha Hauer