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3 Commits

Author SHA1 Message Date
Sascha Hauer 09821fba06 ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority 
This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
 2014-03-29 07:57:53 +01:00
Philipp Zabel 073fb20afe ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX 
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
 2014-03-19 16:20:26 +01:00
Sascha Hauer 4f2c6d4596 mfd: Add i.MX6 iomux gpr header file 
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
 2012-12-07 12:19:45 +01:00