since 99e72c8bbd on an i.MX51 based board,
I get : "phy0: Link is up - 1000/Full". It seems miidev tries to probe
the PHY to early and gets 0x3ffff which leads to the wrong capabilities
setting.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
miidev_wait_aneg() polled the wrong bit, so link detection did fail on
boards where the PHY had to come out of a powerdown mode.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The dump generated by "md -w -s /dev/phy0"
suggests individual registers need to be
addressed by byte offset, not by register number.
E.g. to set the autonegotiation advertisement register
for 10Mbit only, use "mw -w -d /dev/phy0 8+2 0x0061".
The current mix of offset == register number, but
count == byte count is unintuitive.
Also, to be consistent with "md" on /dev/mem, round up
the count so "8+1" also works to access one register.
However, no attempt is made to do read-modify-write
single byte writes.
Signed-off-by: Johannes Stezenbach <js@sig21.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Check if the PHY is really accessible (e.g. the
PHY address is correct) during probe.
Signed-off-by: Johannes Stezenbach <js@sig21.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The auto negotiation result is the intersect
of the advertised abilities and the link partner abilities.
Signed-off-by: Johannes Stezenbach <js@sig21.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some phys need board specific fixups. To be able to do this
from board code add mii_open/mii_close functions so that the
board can use the regular mii_read/mii_write functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Wait until the reset bit is actually cleared instead of some
arbitrary delay (which caused problems with a PHY which was in some
energy saving mode).
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
First check the status at least once, then do timeout checks. Minor
cleanups also.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently, we can only print the phy_status. Factor out the routine to
get the status, so we can query it from fec drivers and configure
accordingly. Needed because mx28 needs a special bit set for 10Mbit.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Ethernet PHY devices have 32 registers, each 16 bits wide. Thus, the size of
the phy device should be 64 bytes.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
now we need to set the dev id to -1
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this rework is done in order to add a phylib and allow to have phy driver support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Eric Bénard
Wolfram Sang
Sascha Hauer
Johannes Stezenbach
Baruch Siach
Jean-Christophe PLAGNIOL-VILLARD