The current fixup code is slightly wrong, and only works when the
root address cell number is one.
However, Armada XP has a root address cell number of two. In this case
we are currently applying the fixup on the child high base address,
while it should be applied on the child low base address.
Fix it and add some detailed explanation to avoid having to figure this
out each time.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for the RTC unit on Ingenic JZ4740, JZ475x and JZ477x SoCs.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Current ds1307 rtc driver supports only ds1307 and ds1338 chips;
it has no nvram support at the moment.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
[voice.shen@atmel.com: apply this patch from Matteo Fortini for
sama5d3xek to sama5d3_xplained board]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Most diffstat comes from refreshing the config. The only real change
is that the NAND xload update handler is enabled now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We interpret the ECC option "bch8" as OMAP_ECC_BCH8_CODE_HW, but the
Kernel uses OMAP_ECC_BCH8_CODE_HW_ROMCODE in this case instead. To make
the interpretation of the ti,nand-ecc-opt property compatible to the
Kernel we have to use OMAP_ECC_BCH8_CODE_HW_ROMCODE for "bch8"
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for 256MB and 128MB RAM configurations of the
phyCORE-AM335x. This is done as new images.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- use am335x_barebox_entry() to remove the need for hardcoded SDRAM
size
- remove hardcoded memory settings from device tree since there are
different memory sizes available for this board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a function which reads back the SDRAM controller settings.
This is used in a AM33xx specific barebox entry function and a
SDRAM driver which registers a SDRAM memory bank.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Check for the return value of devfs_add_partition with IS_ERR.
Otherwise we dereference a NULL pointer when devfs_add_partition
fails.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If an external environment storage should be used in very rare and special cases,
the intentional behaviour should be to ignore the external environment and always
fall back to the built-in environment. By storing an empty "to be ignored" environment
into the external environment a confusing error message about invalid CRC sums will go
away and still the built-in environment is used.
With this new option we can force the intentional behaviour.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In order to be able to mark an stored envfs image with special features
(intentional ignore for example), we now can feed forward these flags.
By forwarding a '0' for the flags nothing changes because the envfs superblock
was already allocated with xzalloc.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a simple flag to envfs to be able to mark an external environment as
"not to be used".
This change should not affect existing systems, because the current envfs
implementation ensures the 'flags' member in the envfs master block is always
zeroed.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Both parameters can be omitted and DIRECTORY can be omitted, but the
DIRECTORY parameter requires the ENVFS parameter as well.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also move reset_cpu() for jz4755 SoC from platform code
into the new driver code.
At the moment mach-xburst lacks clk support so jz4740 watchdog
driver looks like a template. We can improve jz4740 watchdog
driver later after adding clk support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Change Product Data validity checking to ensure that support can
be provided for 8-bit and 16-bit EEPROM devices.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With an update of the am33xx.dtsi (commit 9313920df6) the mdio and mac
nodes are not enabled on default any more. Enable them explicit
in the board dts now.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here is compiler's message:
drivers/led/led-triggers.c:148:5: warning: no previous prototype for 'trigger_init' [-Wmissing-prototypes]
int trigger_init(void)
^
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here is a sample crash log on Ritmix RZX-50:
barebox:/ trigger
0: panic
1: heartbeat
2: net rx
3: net tx
4: net
5: default on (led 0)
barebox:/ trigger -d 5
...
Ooops, TLB miss on store!
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This driver is also used for Allwinner SoCs I2C controllers.
Ported from linux-3.15.
The most notable barebox driver version changes:
* drop platform device stuff;
* drop "allwinner,sun*" stuff;
* drop message offloading support;
* add reg-io-width devicetree parameter to use driver
with byte-oriented controller versions.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
On Armada XP:
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Based on Linux's support by Thomas Petazzoni:
commit b9d12085f2f531fdea67f0361564e0812696227c
Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Tue Apr 15 15:50:19 2014 +0200
net: phy: add minimal support for QSGMII PHY
This commit adds the necessary definitions for the PHY layer to
recognize "qsgmii" as a valid PHY interface. A QSMII interface, as
defined at
http://en.wikipedia.org/wiki/Media_Independent_Interface#Quad_Serial_Gigabit_Media_Independent_Interface,
is "is a method of combining four SGMII lines into a 5Gbit/s
interface. QSGMII, like SGMII, uses LVDS signalling for the TX and RX
data and a single LVDS clock signal. QSGMII uses significantly fewer
signal lines than four SGMII busses."
This type of MAC <-> PHY connection might require special handling on
the MAC driver side, so it should be possible to express this type of
MAC <-> PHY connection, for example in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This property is wrongly documented as 'optional', although all the
ethernet units need a clock to be enabled in order to access the MDIO
interface. For that reason, this commit makes the property a required
one and fails to probe the device, when a clock is not properly provided.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In addition to the standard 'phy-handle' devicetree property, the binding
specifies two properties, which are considered obsolete: 'phy' and 'phy-device'.
This commit adds support for them in of_mdio_find_phy().
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the functional driver itself, it also adds SoC specific PHY
setup required for PCIe. Currently, only Armada 370 is fully supported.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When using more than one PCI bus, we have to assign unique numbers
to each bus. Use an auto-incremented bus index and assign it to
each registered bus. Also, allow the PCI host controller to update
internal registers by calling set_busno with assigned bus number.
While at it, add pci_controller struct to set_busno callback,
add a back reference to pci_controller to pci_bus, and clean up
unused left-overs from Linux import.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Disable access to PCI devices I/O and memory regions while
mangling BAR registers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As soon as pci_register_device is called, a potential driver
will access its registers. This requires BARs to be set up
properly, so move pci_register_device after BAR setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
