Also move reset_cpu() for jz4755 SoC from platform code
into the new driver code.
At the moment mach-xburst lacks clk support so jz4740 watchdog
driver looks like a template. We can improve jz4740 watchdog
driver later after adding clk support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Change Product Data validity checking to ensure that support can
be provided for 8-bit and 16-bit EEPROM devices.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With an update of the am33xx.dtsi (commit 9313920df6) the mdio and mac
nodes are not enabled on default any more. Enable them explicit
in the board dts now.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here is compiler's message:
drivers/led/led-triggers.c:148:5: warning: no previous prototype for 'trigger_init' [-Wmissing-prototypes]
int trigger_init(void)
^
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here is a sample crash log on Ritmix RZX-50:
barebox:/ trigger
0: panic
1: heartbeat
2: net rx
3: net tx
4: net
5: default on (led 0)
barebox:/ trigger -d 5
...
Ooops, TLB miss on store!
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This driver is also used for Allwinner SoCs I2C controllers.
Ported from linux-3.15.
The most notable barebox driver version changes:
* drop platform device stuff;
* drop "allwinner,sun*" stuff;
* drop message offloading support;
* add reg-io-width devicetree parameter to use driver
with byte-oriented controller versions.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
On Armada XP:
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Based on Linux's support by Thomas Petazzoni:
commit b9d12085f2f531fdea67f0361564e0812696227c
Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Tue Apr 15 15:50:19 2014 +0200
net: phy: add minimal support for QSGMII PHY
This commit adds the necessary definitions for the PHY layer to
recognize "qsgmii" as a valid PHY interface. A QSMII interface, as
defined at
http://en.wikipedia.org/wiki/Media_Independent_Interface#Quad_Serial_Gigabit_Media_Independent_Interface,
is "is a method of combining four SGMII lines into a 5Gbit/s
interface. QSGMII, like SGMII, uses LVDS signalling for the TX and RX
data and a single LVDS clock signal. QSGMII uses significantly fewer
signal lines than four SGMII busses."
This type of MAC <-> PHY connection might require special handling on
the MAC driver side, so it should be possible to express this type of
MAC <-> PHY connection, for example in the Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This property is wrongly documented as 'optional', although all the
ethernet units need a clock to be enabled in order to access the MDIO
interface. For that reason, this commit makes the property a required
one and fails to probe the device, when a clock is not properly provided.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In addition to the standard 'phy-handle' devicetree property, the binding
specifies two properties, which are considered obsolete: 'phy' and 'phy-device'.
This commit adds support for them in of_mdio_find_phy().
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the functional driver itself, it also adds SoC specific PHY
setup required for PCIe. Currently, only Armada 370 is fully supported.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When using more than one PCI bus, we have to assign unique numbers
to each bus. Use an auto-incremented bus index and assign it to
each registered bus. Also, allow the PCI host controller to update
internal registers by calling set_busno with assigned bus number.
While at it, add pci_controller struct to set_busno callback,
add a back reference to pci_controller to pci_bus, and clean up
unused left-overs from Linux import.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Disable access to PCI devices I/O and memory regions while
mangling BAR registers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As soon as pci_register_device is called, a potential driver
will access its registers. This requires BARs to be set up
properly, so move pci_register_device after BAR setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type
indicates a 64-bit BAR we have to skip the next BAR register.
While at it, also set proper IORESOURCE flags for I/O and
32b MEM.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A resource_size is defined as res->end - res->start + 1. Marvell
MBUS driver gets some ranges from DT as start and size but mis-calculates
end of range. This fixes 4 occurences of those mistakes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM946E-S is used in the DIGIC family SoCs.
ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:
.word 0x41009400 @ ARM94x
.word 0xff00ff00
W(b) __armv4_mpu_cache_on
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On at91sam9n12 soc, it has pllb, while on sama5d3 soc,
it doesn't has pllb.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This reimplements the history functions in readline.
- Use regular lists instead of homegrown list implementation
- Allocate history strings dynamically instead of copying strings
to fixed buffers without checking the size
- saves us an initcall
- slightly smaller
- no longer add duplicates to the history
- when moving past the last history entry print an empty line
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a compatible to this driver so it can be added through devicetree.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also drop nowhere defined CONFIG_EHCI_DESC_BIG_ENDIAN.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a driver for PCI-attached xHCI controllers.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for xHCI USB 3.0 host controllers found on various
SoCs and PCI devices. Currently, the driver only supports the virtual
USB 2.0 ports of the host controller, so if you plan to use USB 3.0
devices, put a USB 2.0 cable in between.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This imports {lower,upper}_32_bits defines to allow to get upper
and lower 32b part of a 64b number.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
EHCI HCD has a private version of min3() determining the smallest
number out of 3. We already have min()/max() imported from Linux,
also get min3()/max3() and use it instead of EHCI's private one.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
USB core isn't too strict about allocation/deallocation and
add/remove sequences of usb devices. Especially, error paths
and device tear-down are kind of broken and cause hangs on
failing usb device detect.
This patch improves the situation by introducing a
usb_free_device() that tears down allocated resources by
usb_alloc_new_device(). usb_remove_device() now only deals
with resources that have been added by usb_new_device().
Also, error handling is fixed or improved to ensure that no
devices are unregistered that have not been previously
registered.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adding a usb device increases dev_index every time a new device is
allocated. Removing a usb device does not decrease again, of course.
As we print the number of detected usb devices after each usb bus
scan based on dev_index, we cannot trust dev_index here. Keep track
of the correct number of (currently) detected usb devices by
introducing an independent dev_count that gets increased on detect
and decreased on remove.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
New usb devices are added to a list of usb devices, but when removing
the corresponding usb_device it was not removed from that list. Fix it
by deleting it properly from the usb_device_list.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a limited board support for the Freescale P1010RDB.
The board boots from NOR and output the prompt to the serial port
at 115200 bauds. All 3 Ethernet ports are supported by the gianfar
driver. I2C devices are accessible on both bus and the memory is
initialised by the 85xx DDR driver.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Antony Pavlov
Renaud Barbier
Teresa Gámez
Matteo Fortini
Ezequiel Garcia
Sebastian Hesselbarth
Sascha Hauer
Bo Shen
Markus Pargmann