We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a DT init function to clk-fixed and corresponding CLK_OF_DECLARE
to put it into the DT clock provider table.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This add barebox versions of of_clk_init for parsing and registering
clock providers from DT. Also, a macro CLK_OF_DECLARE is added, that
allows to put init callbacks into its own section that can be linked
in the binary.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The SoCFPGA currently has all clocks described in the devicetree which
makes common clock support a straight forward task.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
since the switch to common clock, ethernet driver doesn't works and
and access to the network leads to :
eth0: Read MDIO failed...
unable to handle NULL pointer dereference at address 0x000000c7
The problem is that bit 31 (SLEEP) of register HW_CLKCTRL_ENET is kept
to its default value (1) which means : "put Ethernet block in sleep mode.
CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET0(1)_TX are gated off.
Ethernet can be wakeup remotely in sleep mode"
In that case the FEC don't get its clock.
This patch fix the problem by toggling this bit when FEC's clock is
enabled.
Tested on i.MX28EVK.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds of_clk_providers for core clocks and clock gates found on
Marvell MVEBU SoCs (Armada 370, Armada XP, Dove, and Kirkwood).
It is based on Linux clock providers with clock flags removed, as they
are not used on Barebox.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format.
No functional changes.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When changing the rates of the ssp clocks we have to poll the
busy bit, but only when they are enabled. The current code can
not check this properly since the gates are registered as children
of the dividers. This has the effect that when the gate is disabled
the busy bit will be set forever resulting in a freezed system.
Fix this by making the gates parents of the dividers which allows
clk_is_enabled to return the correct result.
The Kernel has the same problem, but here the busy polling is
limited to 10ms, so probably noone noticed this.
The datasheet mentions that the ssp dividers shall only be changed
when the clocks are enabled. The kernel and barebox currently ignore
this. I don't know what effect violating this rule has.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only UART clocks are included for now, but the code should cover
other peripherals needs, too.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This removes the existing Tegra CAR driver and replaces it with code
ported from the Linux clock framework.
In the current state only the relevant PLLs are supported, but this is
no functional regression from the existing code.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows to reuse the clk gate code within other clocks.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Taken from the Linuxkernel with some small adjustments for barebox.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MXS needs some special MXS specific clock types:
- pll
- ref (fractional divider)
- busy divider (divider with additional busy bit to poll on a rate change)
- lcdif (Combined clock out of a fractional divider, a divider and a gate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On MXS we need to poll the busy bit when changing a clock rate, but only
when the parent clocks are enabled. This exposes the already present
function clk_is_enabled which is suitable for this job.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This allows us to better detect whether a clk is enabled or not.
- If we can ask a clk, ask it. If it's enabled, go on and ask parents
- If we can't ask it, but it can be enabled, depend on the enable_count.
if it's positive, go on and ask parents
- If we can't ask it and it cannot be enabled, assume it is enabled
and ask parents.
This makes the CLK_ALWAYS_ENABLED unnecessary, since the fixed clk now
always returns 1 in its is_enabled callback.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox not contain symbol HAVE_CLK, so remove all references to it.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Current barebox clk framework allow disable any clock
and there is no means to prevent that.
But there are the clocks that can't be disabled
by software at all.
This patch allow registration of a clock immune to clk_disable().
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Checking for invalid clocks on function entry allows users
to for example do a clk_set_rate(clk_lookup("myclk"), x) without
checking for validity of the result of clk_lookup first.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds barebox common clk support loosely based on the Kernel common
clk support. differences are:
- barebox does not need prepare/unprepare
- no parent rate propagation for set_rate
- struct clk is not really encapsulated from the drivers
Along with the clk support we have support for some basic clk building
blocks:
- clk-fixed
- clk-fixed-factor
- clk-mux
- clk-divider
clk-fixed and clk-fixed-factor are completely generic, clk-mux and clk-divider
are currently the way i.MX muxes/dividers are implemented.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Most clock/device associations can be done based on the physical
base address of the corresponding device. So instead of depending
on string matching add an optional possibility to associate a clock
lookups with physical addresses. This also has the advantage that
the lookups for devicetree based devices can be identical to the
platform based devices.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as refer in this patch "arm & sh: factorised duplicated clkdev.c"
factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99% in linux
move it also as preparing for the SH adding
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Sascha Hauer
Lucas Stach
Sebastian Hesselbarth
Eric Bénard
Alexander Shiyan
Juergen Beisert
Antony Pavlov
Carlo Caione
Jean-Christophe PLAGNIOL-VILLARD