Checking the status field of the qTD token in the current code
do not take into acount cases where endpoint stall (halted) bit
is set together with XactErr status bit. As a result clearing
stall on an endpoint won't be done if this status bit was also
set. Check for halted bit and report USB_ST_STALLED status
if the host controller also indicates endpoit stall condition.
From u-boot by Anatolij Gustschin <agust@denx.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EfikaSB has a bug requiring to write to an ULPI register after
powerup. It doesn't seem that this this bug is present on any other
hardware, so add a workaround directly into the driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EHCI core often is part of a otg core. Allow it to be registered
separately from another driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The FSF address has changed in the past. Instead of updating it
each time the address changes, just drop it completely treewide.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We do not need to invalidate the cache in the poll loop anymore
since the corresponding bit is now in a dma coherent area. Instead,
flush cache before hardware operation and invalidate afterwards. Put
the corresponding code inline since it's shorter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There's no point in syncing them manually. Instead, use
dma_alloc_coherent and skip the manual flushing/invalidating.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is based on the following U-Boot commit:
commit 5f4b4f2fed3ab8590c8c06b78642f8c1467acacf
Author: Vincent Palatin <vpalatin@chromium.org>
Date: Mon Dec 5 14:52:22 2011 -0800
ehci: speed up initialization
According to EHCI specification v1.0, the controller should stabilize
the power on a port at most 20 ms after the port power bit transition.
So, we put this setting in the virtual descriptor corresponding field,
(bPwrOn2PwrGood = 10 => 10 x 2ms = 20ms), this saves about 500ms at each
controller initialization/enumeration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
for chache handling the ehci driver iterates over the hardware lists
of QHs/TDs. As we have a fixed number of maximum entries in this lists
we can allocate them as arrays and and clean/invalidate the arrays
instead which is much simpler. While at it, move the allocation to
ehci_probe so that we do not lose memory each time ehci_init is called.
Also, use memalign to allocate the QHs/TDs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pass the hccr and hcor register base via resource
instroduce add_generic_usb_echi_device with hccr = base + 0x100 and
hcor = base + 0x140
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
move to linux usb driver organisation
as following
drivers/usb/core
drivers/usb/gadget
drivers/usb/host
drivers/usb/otg
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Alexander Shiyan
Sascha Hauer
Jean-Christophe PLAGNIOL-VILLARD
Antony Pavlov
Rosen Kolev
Michael Grzeschik