If we have two discontinuous memory banks we want to move
the malloc area into the upper bank by default to leave as
much free space in the lower bank, where we have to place
kernel, oftree and initrd.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Mostly to make it clear that boarddata needs to be
something we can dereference.
As this is a pretty invasive change, use the opportunity
to make the signature 64bit safe.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To reduce the devicetree files for one board with different memory sizes the
memory size can be read back from i.MX6.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A lot of files rely on include/driver.h including include/of.h (and
this including include/errno.h. include the files explicitly so we can
eventually get rid of including of.h from driver.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On some i.MX SoCs the SDRAM controller has chipselect 2 enabled
by reset default. This confuses our SDRAM size detection. We
already have a fix for this in place. This patch adds the fix
for i.MX35 which needs it aswell. Also since we now detect the
SDRAM size in the SoC specific entry functions we have to apply
the fixup there, too.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Additionally to the generic entry point the i.MX specific ones
calculate the SDRAM size automatically so the boards do not have
to care.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX27/31 have the second chip select enabled by reset default.
This can be considered as a hardware bug, because even boards which
need this settings cannot work out of reset because of the missing
initialization sequence. Detect this reset default setting and disable
this chipselect then to be able to properly detect the SDRAM size.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The code initializing the SDRAM controller is not at the same
place where SDRAM is registered with barebox. To reduce the
risk of registering wrong SDRAM sizes this patch adds a
driver for the ESDCTL which reads back the configured SDRAM
size and registers the memory found with barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>