The SoCFPGA currently has all clocks described in the devicetree which
makes common clock support a straight forward task.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds of_clk_providers for core clocks and clock gates found on
Marvell MVEBU SoCs (Armada 370, Armada XP, Dove, and Kirkwood).
It is based on Linux clock providers with clock flags removed, as they
are not used on Barebox.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This removes the existing Tegra CAR driver and replaces it with code
ported from the Linux clock framework.
In the current state only the relevant PLLs are supported, but this is
no functional regression from the existing code.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MXS needs some special MXS specific clock types:
- pll
- ref (fractional divider)
- busy divider (divider with additional busy bit to poll on a rate change)
- lcdif (Combined clock out of a fractional divider, a divider and a gate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds barebox common clk support loosely based on the Kernel common
clk support. differences are:
- barebox does not need prepare/unprepare
- no parent rate propagation for set_rate
- struct clk is not really encapsulated from the drivers
Along with the clk support we have support for some basic clk building
blocks:
- clk-fixed
- clk-fixed-factor
- clk-mux
- clk-divider
clk-fixed and clk-fixed-factor are completely generic, clk-mux and clk-divider
are currently the way i.MX muxes/dividers are implemented.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as refer in this patch "arm & sh: factorised duplicated clkdev.c"
factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99% in linux
move it also as preparing for the SH adding
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>