Here is the warning message:
drivers/net/usb/asix.c:427:5: warning: no previous prototype for 'asix_rx_fixup_internal' [-Wmissing-prototypes]
int asix_rx_fixup_internal(struct usbnet *dev, void *buf, int len,
^
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ax_skb receive buffer unalignment leads to consequent
unalignment data access in network stack routines,
especially in net_checksum().
By-turn unalignment data accesses lead to performance penalty.
Moreover on classic MIPS CPUs without hardware unalignment access
support this leads to undesirable exceptions.
At the moment barebox on MIPS can't parry these unalignment access
exceptions, so the Asix USB Ethernet chips, that need receive
fixup workaround, are completely unusable on MIPS without this patch.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Hello!
This patch adds support for USB ethernet adapter D-Link DUB-E100 H/W Rev C1. I tested this on
Beagleboneblack Rev A6A and our custom h/w based on i.mx6 Phytec phycore module. More
information about the adapter is here:
http://us.dlink.com/products/connect/high-speed-usb-2-0-fast-ethernet-adapter/
Signed-off-by: Mayur Nande <mayur.nande@medel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ASIX AX88772B started to pack data even more tightly. Packets and the ASIX packet
header may now cross URB boundaries. To handle this we have to introduce
some state between individual calls to asix_rx_fixup().
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
[ Rolf: ported from kernel to barebox 2014.09.0 ]
Signed-off-by: Rolf Evers-Fischer <embedded24@evers-fischer.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The AX88772B uses only 11 bits of the header for the actual size. The other bits
are used for something else. This causes dmesg full of messages:
asix_rx_fixup() Bad Header Length
This patch trims the check to only 11 bits. I believe on older chips, the
remaining 5 top bits are unused.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adapt phylib from linux
switch all the driver to it
reimplement mii bus
This will allow to have
- phy drivers
- to only connect the phy at then opening of the device
- if the phy is not ready or not up fail on open
Same behaviour as in linux and will allow to share code and simplify porting.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
this rework is done in order to add a phylib and allow to have phy driver support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
