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10 Commits

Author SHA1 Message Date
Sascha Hauer cad14480bf ARM: create a second level page table entry for the exception vectors
Often enough the exception vectors are not on TEXT_BASE (for example
on i.MX SoCs in internal boot mode), so the board specific code did
not map the exception vectors to 0x0 but whatever happens to be on
TEXT_BASE. Also, the current section-only mapping requires the
exception vectors to be on a 1MB boundary.
Instead, create the possibility to create second level tables and
use this to map a copy of the exception vectors in a board
independent way.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-03-10 14:49:47 +01:00
Sascha Hauer 1c33aacf8a ARM: use memalign to allocate page table
We have the proper function for getting aligned memory, so use it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-03-08 12:33:20 +01:00
Krzysztof Halasa c5baa0edc4 Fix error handling with malloc, memalign etc. Introduce xmemalign().
The idea is to panic() when there is no memory available for normal
operation. Exception: code which can consume arbitrary amount of RAM
(example: files allocated in ramfs) must report error instead of panic().

This patch also fixes code which didn't check for NULL from malloc() etc.

Usage: malloc(), memalign() return NULL when out of RAM.
xmalloc(), xmemalign() always return non-NULL or panic().

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-01-07 10:21:22 +01:00
Sascha Hauer cdd5db42ef ARM mmu: Call __mmu_cache_flush instead of hardcoded v4/v5 only function
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-10-11 13:22:14 +02:00
Sascha Hauer 51b4009f3c ARM: use memalign in dma_alloc_coherent to assure alignment
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-05-03 15:02:03 +02:00
Sascha Hauer be00ed538c add l2x0 cache support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-03-30 14:15:04 +02:00
Sascha Hauer bcaabae0f6 ARM: Add a wrapper around dma_* functions
This is a preparation to add second level cache support.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-03-30 14:15:04 +02:00
Sascha Hauer 3f1bf1f058 Use cache functions from kernel
These cache functions have been extracted from
arch/arm/boot/compressed/head.S. The old code only worked
properly on ARMv4. Tested on ARMv4, ARMv5, ARMv6 hardware.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-02-01 17:23:40 +01:00
Sascha Hauer 3820307eb0 rename dma macros
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-09-25 13:34:57 +02:00
Sascha Hauer e2c8e8a180 Add MMU support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-08-19 10:51:30 +02:00