When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.
This patch also extends the read routine to support more than four address
cycles on demand.
BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With this patch barebox can now be booted from RAM, NOR and NAND on the
mini2440 platform. 'CONFIG_S3C24XX_NAND_BOOT' must still be 'y' to be able to
boot from NAND.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The default configuration of the current 2.6.37 kernel uses a flash based BBT.
So, barebox must also use one, to be in sync with the kernel about bad blocks
in the flash.
Due to the used OOB layout, the generic BBT description coming with the
framework can be used.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There is no rule how to connect the SDRAMs to the two clocks signales the CPU
provides. Some boards are using them on a per bank base, some others on a per
chip base. So, the check for the enabled second clock cannot be used to detect
if the second SDRAM bank is populated.
A better way is to check the MT bits of the second SDRAM bank register. When
the init code sets these bits to '00' the second bank is not used for SDRAM
and gets ignored.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This work is mainly based on a9m2440 board implementation
from Juergen Beisert <jbe@pengutronix.de>. Functionality
was tested only running barebox from ram. Loading to flash
and booting will not work because missing lowlevel_init
functionality (lack of jtag debugger on my side ;)).
Signed-off-by: Marek Belisko <marek.belisko@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds genetic GPIO support to all S3C2440 processor based systems.
Also it adds definitions to setup the pin multiplexer in a way the other
architectures do.
Note: Tested on a S3C2440 based system only. But should work on an S3C2410, too.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adding MCI card support for S3C2440 CPUs. This is for reference only, as there
is currently no user in the barebox tree. Maybe one with access to the A9M2440
development kit can check it on his/her system.
Checked here with my own S3C2440 based system which is not in the barebox tree.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Following steps lead to compilation error (barebox v2010.09.0):
1. make a9m2440_defconfig (or a9m2410) ARCH=arm
2. make CROSS_COMPILE=arm-linux- ARCH=arm
This patch should fix problems.
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this will allow each arch to handle the boards more simply and depending on
there need
the env var BOARD will refer to the current board dirent
for sandbox as we have only one board the board dirent is arch/sandbox/board
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
instead of select first the board which will select the arch, now
first choice the arch to filter the possible boards
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
instead of select first the board which will select the arch, now
first choice the arch to filter the possible boards
as it's already done for omap
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
There is no really generic way to configure the S3C2440 CPU with fits to all
possible baseboards. This patch separates things into the CPU card related and
baseboard related things. This ensures to be able to configure things for
each possible baseboard without modifying/patching the main card source.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
This patch adds code to determine the current available SDRAM size. It relies
on other routines setting up the SDRAM controller, because it only read back
their settings.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
It includes a
- driver for the internal UART
- driver for the internal NAND controller
- support to boot from NAND
- PLL handling
- SDRAM initialisation
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>