638 lines
16 KiB
C
638 lines
16 KiB
C
/*
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* SMSC LAN9[12]1[567] Network driver
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <malloc.h>
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#include <init.h>
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#include <xfuncs.h>
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#include <errno.h>
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#include <clock.h>
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#include <io.h>
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#include <smc911x.h>
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#include <linux/phy.h>
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#include "smc911x.h"
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struct smc911x_priv {
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struct eth_device edev;
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struct mii_bus miibus;
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void __iomem *base;
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int shift;
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int generation;
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unsigned int flags;
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unsigned int idrev;
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unsigned int using_extphy;
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unsigned int phy_mask;
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u32 (*reg_read)(struct smc911x_priv *priv, u32 reg);
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void (*reg_write)(struct smc911x_priv *priv, u32 reg, u32 val);
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};
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#define DRIVERNAME "smc911x"
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#define __smc_shift(priv, reg) ((reg) << ((priv)->shift))
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static inline u32 smc911x_reg_read(struct smc911x_priv *priv, u32 reg)
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{
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return priv->reg_read(priv, reg);
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}
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static inline u32 __smc911x_reg_readw(struct smc911x_priv *priv, u32 reg)
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{
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return ((readw(priv->base + reg) & 0xFFFF) |
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((readw(priv->base + reg + 2) & 0xFFFF) << 16));
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}
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static inline u32 __smc911x_reg_readl(struct smc911x_priv *priv, u32 reg)
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{
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return readl(priv->base + reg);
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}
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static inline u32
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__smc911x_reg_readw_shift(struct smc911x_priv *priv, u32 reg)
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{
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return (readw(priv->base +
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__smc_shift(priv, reg)) & 0xFFFF) |
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((readw(priv->base +
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__smc_shift(priv, reg + 2)) & 0xFFFF) << 16);
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}
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static inline u32
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__smc911x_reg_readl_shift(struct smc911x_priv *priv, u32 reg)
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{
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return readl(priv->base + __smc_shift(priv, reg));
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}
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static inline void smc911x_reg_write(struct smc911x_priv *priv, u32 reg,
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u32 val)
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{
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priv->reg_write(priv, reg, val);
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}
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static inline void __smc911x_reg_writew(struct smc911x_priv *priv, u32 reg,
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u32 val)
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{
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writew(val & 0xFFFF, priv->base + reg);
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writew((val >> 16) & 0xFFFF, priv->base + reg + 2);
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}
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static inline void __smc911x_reg_writel(struct smc911x_priv *priv, u32 reg,
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u32 val)
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{
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writel(val, priv->base + reg);
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}
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static inline void
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__smc911x_reg_writew_shift(struct smc911x_priv *priv, u32 reg, u32 val)
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{
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writew(val & 0xFFFF,
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priv->base + __smc_shift(priv, reg));
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writew((val >> 16) & 0xFFFF,
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priv->base + __smc_shift(priv, reg + 2));
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}
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static inline void
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__smc911x_reg_writel_shift(struct smc911x_priv *priv, u32 reg, u32 val)
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{
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writel(val, priv->base + __smc_shift(priv, reg));
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}
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static int smc911x_mac_wait_busy(struct smc911x_priv *priv)
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{
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uint64_t start = get_time_ns();
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while (!is_timeout(start, MSECOND)) {
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if (!(smc911x_reg_read(priv, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
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return 0;
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}
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printf("%s: mac timeout\n", __FUNCTION__);
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return -1;
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}
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static u32 smc911x_get_mac_csr(struct eth_device *edev, u8 reg)
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{
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struct smc911x_priv *priv = edev->priv;
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ulong val;
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smc911x_mac_wait_busy(priv);
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smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY |
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MAC_CSR_CMD_R_NOT_W | reg);
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smc911x_mac_wait_busy(priv);
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val = smc911x_reg_read(priv, MAC_CSR_DATA);
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return val;
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}
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static void smc911x_set_mac_csr(struct eth_device *edev, u8 reg, u32 data)
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{
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struct smc911x_priv *priv = edev->priv;
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smc911x_mac_wait_busy(priv);
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smc911x_reg_write(priv, MAC_CSR_DATA, data);
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smc911x_reg_write(priv, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
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smc911x_mac_wait_busy(priv);
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}
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static int smc911x_get_ethaddr(struct eth_device *edev, unsigned char *m)
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{
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unsigned long addrh, addrl;
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addrh = smc911x_get_mac_csr(edev, ADDRH);
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addrl = smc911x_get_mac_csr(edev, ADDRL);
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m[0] = (addrl ) & 0xff;
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m[1] = (addrl >> 8 ) & 0xff;
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m[2] = (addrl >> 16 ) & 0xff;
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m[3] = (addrl >> 24 ) & 0xff;
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m[4] = (addrh ) & 0xff;
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m[5] = (addrh >> 8 ) & 0xff;
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/* we get 0xff when there is no eeprom connected */
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if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff)
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return -1;
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return 0;
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}
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static int smc911x_set_ethaddr(struct eth_device *edev, unsigned char *m)
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{
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unsigned long addrh, addrl;
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addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24;
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addrh = m[4] | m[5] << 8;
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smc911x_set_mac_csr(edev, ADDRH, addrh);
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smc911x_set_mac_csr(edev, ADDRL, addrl);
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return 0;
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}
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static int smc911x_phy_read(struct mii_bus *bus, int phy_addr, int reg)
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{
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struct eth_device *edev = bus->priv;
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while (smc911x_get_mac_csr(edev, MII_ACC) & MII_ACC_MII_BUSY);
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smc911x_set_mac_csr(edev, MII_ACC, phy_addr << 11 | reg << 6 |
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MII_ACC_MII_BUSY);
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while (smc911x_get_mac_csr(edev, MII_ACC) & MII_ACC_MII_BUSY);
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return smc911x_get_mac_csr(edev, MII_DATA);
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}
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static int smc911x_phy_write(struct mii_bus *bus, int phy_addr,
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int reg, u16 val)
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{
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struct eth_device *edev = bus->priv;
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while (smc911x_get_mac_csr(edev, MII_ACC) & MII_ACC_MII_BUSY);
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smc911x_set_mac_csr(edev, MII_DATA, val);
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smc911x_set_mac_csr(edev, MII_ACC,
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phy_addr << 11 | reg << 6 | MII_ACC_MII_BUSY |
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MII_ACC_MII_WRITE);
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while (smc911x_get_mac_csr(edev, MII_ACC) & MII_ACC_MII_BUSY);
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return 0;
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}
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/* Switch to external phy. Assumes tx and rx are stopped. */
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static void smsc911x_phy_enable_external(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 hwcfg = smc911x_reg_read(priv, HW_CFG);
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/* Disable phy clocks to the MAC */
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hwcfg &= (~HW_CFG_PHY_CLK_SEL);
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hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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udelay(10); /* Enough time for clocks to stop */
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/* Switch to external phy */
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hwcfg |= HW_CFG_EXT_PHY_EN;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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/* Enable phy clocks to the MAC */
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hwcfg &= (~HW_CFG_PHY_CLK_SEL);
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hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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udelay(10); /* Enough time for clocks to restart */
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/* Switch MDIO/MDC to external PHY */
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hwcfg |= HW_CFG_SMI_SEL;
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smc911x_reg_write(priv, HW_CFG, hwcfg);
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}
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/* Autodetects and enables external phy if present on supported chips.
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* autodetection can be overridden by specifying SMC911X_FORCE_INTERNAL_PHY
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* or SMC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
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static void smsc911x_phy_initialise_external(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 hwcfg = smc911x_reg_read(priv, HW_CFG);
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if (priv->flags & SMC911X_FORCE_INTERNAL_PHY) {
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dev_info(edev->parent, "Forcing internal PHY\n");
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priv->using_extphy = 0;
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} else if (priv->flags & SMC911X_FORCE_EXTERNAL_PHY) {
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dev_info(edev->parent, "Forcing external PHY\n");
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smsc911x_phy_enable_external(edev);
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priv->using_extphy = 1;
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} else if (hwcfg & HW_CFG_EXT_PHY_DET) {
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dev_info(edev->parent,
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"HW_CFG EXT_PHY_DET set, using external PHY\n");
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smsc911x_phy_enable_external(edev);
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priv->using_extphy = 1;
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} else {
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dev_info(edev->parent,
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"HW_CFG EXT_PHY_DET clear, using internal PHY\n");
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priv->using_extphy = 0;
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}
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}
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static int smc911x_phy_reset(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 reg;
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reg = smc911x_reg_read(priv, PMT_CTRL);
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reg &= 0xfcf;
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reg |= PMT_CTRL_PHY_RST;
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smc911x_reg_write(priv, PMT_CTRL, reg);
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mdelay(100);
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return 0;
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}
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static void smc911x_reset(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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uint64_t start;
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/* Take out of PM setting first */
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if (smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY) {
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/* Write to the bytetest will take out of powerdown */
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smc911x_reg_write(priv, BYTE_TEST, 0);
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start = get_time_ns();
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while(1) {
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if ((smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY))
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break;
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if (is_timeout(start, 100 * USECOND)) {
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dev_err(&edev->dev,
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"timeout waiting for PM restore\n");
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return;
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}
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}
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}
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/* Disable interrupts */
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smc911x_reg_write(priv, INT_EN, 0);
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smc911x_reg_write(priv, HW_CFG, HW_CFG_SRST);
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start = get_time_ns();
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while(1) {
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if (!(smc911x_reg_read(priv, E2P_CMD) & E2P_CMD_EPC_BUSY))
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break;
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if (is_timeout(start, 10 * MSECOND)) {
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dev_err(&edev->dev, "reset timeout\n");
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return;
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}
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}
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/* Reset the FIFO level and flow control settings */
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smc911x_set_mac_csr(edev, FLOW, FLOW_FCPT | FLOW_FCEN);
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smc911x_reg_write(priv, AFC_CFG, 0x0050287F);
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/* Set to LED outputs */
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smc911x_reg_write(priv, GPIO_CFG, 0x70070000);
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/* Select internal/external PHY */
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switch (priv->idrev & 0xFFFF0000) {
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case 0x01170000:
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case 0x01150000:
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case 0x117A0000:
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case 0x115A0000:
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/* External PHY supported, try to autodetect */
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smsc911x_phy_initialise_external(edev);
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break;
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default:
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dev_dbg(edev->parent, "External PHY is not supported, "
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"using internal PHY\n");
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priv->using_extphy = 0;
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break;
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}
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if (!priv->using_extphy) {
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/* Mask all PHYs except ID 1 (internal) */
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priv->miibus.phy_mask = ~(1 << 1);
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} else {
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/* Mask PHYs as requested (or try all if mask is 0) */
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/* Attn.: first probed PHY is used by phy_device_connect */
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priv->miibus.phy_mask = priv->phy_mask;
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}
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}
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static void smc911x_enable(struct eth_device *edev)
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{
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struct smc911x_priv *priv = edev->priv;
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u32 hw_cfg_phy_settings;
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/* Enable TX */
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hw_cfg_phy_settings = smc911x_reg_read(priv, HW_CFG) & (HW_CFG_PHY_CLK_SEL|HW_CFG_SMI_SEL|HW_CFG_EXT_PHY_EN);
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smc911x_reg_write(priv, HW_CFG, 8 << 16 | HW_CFG_SF | hw_cfg_phy_settings);
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smc911x_reg_write(priv, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
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smc911x_reg_write(priv, TX_CFG, TX_CFG_TX_ON);
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/* no padding to start of packets */
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smc911x_reg_write(priv, RX_CFG, RX_CFG_RX_DUMP);
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}
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static int smc911x_eth_open(struct eth_device *edev)
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{
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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int ret;
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/* use first probed PHY (see also phy_mask) */
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ret = phy_device_connect(edev, &priv->miibus, -1, NULL,
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0, PHY_INTERFACE_MODE_NA);
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if (ret)
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return ret;
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/* Turn on Tx + Rx */
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smc911x_enable(edev);
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return 0;
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}
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static int smc911x_eth_send(struct eth_device *edev, void *packet, int length)
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{
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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u32 *data = (u32*)packet;
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u32 tmplen;
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u32 status;
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uint64_t start;
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smc911x_reg_write(priv, TX_DATA_FIFO,
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TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
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smc911x_reg_write(priv, TX_DATA_FIFO, length);
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tmplen = (length + 3) / 4;
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while(tmplen--)
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smc911x_reg_write(priv, TX_DATA_FIFO, *data++);
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/* wait for transmission */
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start = get_time_ns();
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while (1) {
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if ((smc911x_reg_read(priv, TX_FIFO_INF) &
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TX_FIFO_INF_TSUSED) >> 16)
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break;
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if (is_timeout(start, 100 * MSECOND)) {
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dev_err(&edev->dev, "TX timeout\n");
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return -1;
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}
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}
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/* get status. Ignore 'no carrier' error, it has no meaning for
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* full duplex operation
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*/
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status = smc911x_reg_read(priv, TX_STATUS_FIFO) & (TX_STS_LOC |
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TX_STS_LATE_COLL | TX_STS_MANY_COLL | TX_STS_MANY_DEFER |
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TX_STS_UNDERRUN);
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if(!status)
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return 0;
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dev_err(&edev->dev, "failed to send packet: %s%s%s%s%s\n",
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status & TX_STS_LOC ? "TX_STS_LOC " : "",
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status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
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status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
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status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
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status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
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return -1;
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}
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static void smc911x_eth_halt(struct eth_device *edev)
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{
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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/* Disable TX */
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smc911x_reg_write(priv, TX_CFG, TX_CFG_STOP_TX);
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// smc911x_reset(edev);
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}
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static int smc911x_eth_rx(struct eth_device *edev)
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{
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struct smc911x_priv *priv = (struct smc911x_priv *)edev->priv;
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u32 *data = (u32 *)NetRxPackets[0];
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u32 pktlen, tmplen;
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u32 status;
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if((smc911x_reg_read(priv, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
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status = smc911x_reg_read(priv, RX_STATUS_FIFO);
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pktlen = (status & RX_STS_PKT_LEN) >> 16;
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smc911x_reg_write(priv, RX_CFG, 0);
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tmplen = (pktlen + 2 + 3) / 4;
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while(tmplen--)
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*data++ = smc911x_reg_read(priv, RX_DATA_FIFO);
|
|
|
|
if(status & RX_STS_ES)
|
|
dev_err(&edev->dev, "dropped bad packet. Status: 0x%08x\n",
|
|
status);
|
|
else
|
|
net_receive(edev, NetRxPackets[0], pktlen);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int smc911x_init_dev(struct eth_device *edev)
|
|
{
|
|
smc911x_set_mac_csr(edev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
|
|
MAC_CR_HBDIS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int smc911x_probe(struct device_d *dev)
|
|
{
|
|
struct eth_device *edev;
|
|
struct smc911x_priv *priv;
|
|
uint32_t val;
|
|
int is_32bit, ret;
|
|
struct smc911x_plat *pdata = dev->platform_data;
|
|
|
|
priv = xzalloc(sizeof(*priv));
|
|
is_32bit = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
|
|
if (!is_32bit)
|
|
is_32bit = 1;
|
|
else
|
|
is_32bit = is_32bit == IORESOURCE_MEM_32BIT;
|
|
priv->base = dev_request_mem_region(dev, 0);
|
|
|
|
if (pdata) {
|
|
priv->shift = pdata->shift;
|
|
priv->flags = pdata->flags;
|
|
priv->phy_mask = pdata->phy_mask;
|
|
}
|
|
|
|
if (is_32bit) {
|
|
if (priv->shift) {
|
|
priv->reg_read = __smc911x_reg_readl_shift;
|
|
priv->reg_write = __smc911x_reg_writel_shift;
|
|
} else {
|
|
priv->reg_read = __smc911x_reg_readl;
|
|
priv->reg_write = __smc911x_reg_writel;
|
|
}
|
|
} else {
|
|
if (priv->shift) {
|
|
priv->reg_read = __smc911x_reg_readw_shift;
|
|
priv->reg_write = __smc911x_reg_writew_shift;
|
|
} else {
|
|
priv->reg_read = __smc911x_reg_readw;
|
|
priv->reg_write = __smc911x_reg_writew;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* poll the READY bit in PMT_CTRL. Any other access to the device is
|
|
* forbidden while this bit isn't set. Try for 100ms
|
|
*/
|
|
ret = wait_on_timeout(100 * MSECOND, !smc911x_reg_read(priv, PMT_CTRL) & PMT_CTRL_READY);
|
|
if (!ret) {
|
|
dev_err(dev, "Device not READY in 100ms aborting\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
val = smc911x_reg_read(priv, BYTE_TEST);
|
|
if (val == 0x43218765) {
|
|
dev_dbg(dev, "BYTE_TEST looks swapped, "
|
|
"applying WORD_SWAP");
|
|
smc911x_reg_write(priv, WORD_SWAP, 0xffffffff);
|
|
|
|
/* 1 dummy read of BYTE_TEST is needed after a write to
|
|
* WORD_SWAP before its contents are valid */
|
|
val = smc911x_reg_read(priv, BYTE_TEST);
|
|
|
|
val = smc911x_reg_read(priv, BYTE_TEST);
|
|
}
|
|
|
|
if (val != 0x87654321) {
|
|
dev_err(dev, "no smc911x found on 0x%p (byte_test=0x%08x)\n",
|
|
priv->base, val);
|
|
if (((val >> 16) & 0xFFFF) == (val & 0xFFFF)) {
|
|
/*
|
|
* This may mean the chip is set
|
|
* for 32 bit while the bus is reading 16 bit
|
|
*/
|
|
dev_err(dev, "top 16 bits equal to bottom 16 bits\n");
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
priv->idrev = val = smc911x_reg_read(priv, ID_REV);
|
|
switch (val & 0xFFFF0000) {
|
|
case 0x01180000:
|
|
case 0x01170000:
|
|
case 0x01160000:
|
|
case 0x01150000:
|
|
case 0x218A0000:
|
|
/* LAN911[5678] family */
|
|
priv->generation = val & 0x0000FFFF;
|
|
break;
|
|
|
|
case 0x118A0000:
|
|
case 0x117A0000:
|
|
case 0x116A0000:
|
|
case 0x115A0000:
|
|
/* LAN921[5678] family */
|
|
priv->generation = 3;
|
|
break;
|
|
|
|
case 0x92100000:
|
|
case 0x92110000:
|
|
case 0x92200000:
|
|
case 0x92210000:
|
|
/* LAN9210/LAN9211/LAN9220/LAN9221 */
|
|
priv->generation = 4;
|
|
break;
|
|
|
|
default:
|
|
dev_err(dev, "LAN911x not identified, idrev: 0x%08X\n",
|
|
val);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_info(dev, "LAN911x identified, idrev: 0x%08X, generation: %d\n",
|
|
val, priv->generation);
|
|
|
|
edev = &priv->edev;
|
|
edev->priv = priv;
|
|
|
|
edev->init = smc911x_init_dev;
|
|
edev->open = smc911x_eth_open;
|
|
edev->send = smc911x_eth_send;
|
|
edev->recv = smc911x_eth_rx;
|
|
edev->halt = smc911x_eth_halt;
|
|
edev->get_ethaddr = smc911x_get_ethaddr;
|
|
edev->set_ethaddr = smc911x_set_ethaddr;
|
|
edev->parent = dev;
|
|
|
|
priv->miibus.read = smc911x_phy_read;
|
|
priv->miibus.write = smc911x_phy_write;
|
|
priv->miibus.priv = edev;
|
|
priv->miibus.parent = dev;
|
|
|
|
smc911x_reset(edev);
|
|
smc911x_phy_reset(edev);
|
|
|
|
mdiobus_register(&priv->miibus);
|
|
eth_register(edev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct driver_d smc911x_driver = {
|
|
.name = "smc911x",
|
|
.probe = smc911x_probe,
|
|
};
|
|
device_platform_driver(smc911x_driver);
|