136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
/*
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* barebox - cpu.c CPU specific functions
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*
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* Copyright (c) 2005 blackfin.uclinux.org
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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#include <command.h>
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#include <asm/entry.h>
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#include <asm/cpu.h>
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#include <init.h>
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void __noreturn reset_cpu(unsigned long addr)
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{
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icache_disable();
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__asm__ __volatile__
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("cli r3;"
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"P0 = %0;"
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"JUMP (P0);"
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:
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: "r" (L1_ISRAM)
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);
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/* Not reached */
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while (1);
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}
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void icache_disable(void)
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{
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#ifdef __ADSPBF537__
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if ((*pCHIPID >> 28) < 2)
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return;
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#endif
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__builtin_bfin_ssync();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
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__builtin_bfin_ssync();
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}
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void icache_enable(void)
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{
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unsigned int *I0, *I1;
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int j = 0;
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#ifdef __ADSPBF537__
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if ((*pCHIPID >> 28) < 2)
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return;
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#endif
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/* Before enable icache, disable it first */
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icache_disable();
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I0 = (unsigned int *)ICPLB_ADDR0;
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I1 = (unsigned int *)ICPLB_DATA0;
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/* We only setup instruction caching for barebox itself.
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* This has the nice side effect that we trigger an
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* exception when barebox goes crazy.
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*/
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*I0++ = TEXT_BASE & ~((1 << 20) - 1);
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*I1++ = PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK;
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j++;
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/* Fill the rest with invalid entry */
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for ( ; j < 16 ; j++) {
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debug("filling %i with 0\n",j);
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*I1++ = 0x0;
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}
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__builtin_bfin_ssync();
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asm(" .align 8; ");
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*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
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__builtin_bfin_ssync();
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}
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int icache_status(void)
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{
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unsigned int value;
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value = *(unsigned int *)IMEM_CONTROL;
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if (value & (IMC | ENICPLB))
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return 1;
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else
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return 0;
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}
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static void blackfin_init_exceptions(void)
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{
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*(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
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#ifndef CONFIG_KGDB
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*(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
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#endif
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*(unsigned volatile long *) (EVT_NMI_ADDR) =
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(unsigned volatile long) evt_nmi;
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*(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
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(unsigned volatile long) trap;
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*(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
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(unsigned volatile long) evt_ivhw;
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*(volatile unsigned long *) ILAT = 0;
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asm("csync;");
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*(volatile unsigned long *) IMASK = 0x3f;
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asm("csync;");
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}
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static int blackfin_init_core(void)
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{
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blackfin_init_exceptions();
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icache_enable();
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return 0;
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}
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core_initcall(blackfin_init_core);
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