cbeded2bad
Add DDR3 support into the MPC8xxx DDR driver. To avoid confusion, the function set_ddr_sdram_mode is renamed set_ddr2_sdram_mode. Checking for errors is simplified in the DDR2 DIMM parameters computation to be consistent with DDR3. This code is derived from the files found in directory drivers/ddr/fsl from U-Boot version git-be937b5. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
70 lines
2 KiB
C
70 lines
2 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef DDR2_DIMM_PARAMS_H
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#define DDR2_DIMM_PARAMS_H
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#define EDC_ECC 2
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/* Parameters for a DDR2 dimm computed from the SPD */
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struct dimm_params_s {
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char mpart[19];
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uint32_t n_ranks;
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uint64_t rank_density;
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uint64_t capacity;
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uint32_t data_width;
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uint32_t primary_sdram_width;
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uint32_t ec_sdram_width;
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uint32_t registered_dimm;
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uint32_t device_width;
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/* SDRAM device parameters */
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uint32_t n_row_addr;
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uint32_t n_col_addr;
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uint32_t edc_config; /* 0 = none, 1 = parity, 2 = ECC */
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uint32_t n_banks_per_sdram_device;
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uint32_t burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
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uint32_t row_density;
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uint64_t base_address;
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uint32_t mirrored_dimm;
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uint32_t mtb_ps;
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uint32_t ftb_10th_ps;
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uint32_t taa_ps;
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uint32_t tfaw_ps;
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/* SDRAM clock periods */
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uint32_t tCKmin_X_ps;
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uint32_t tCKmin_X_minus_1_ps;
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uint32_t tCKmin_X_minus_2_ps;
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uint32_t tCKmax_ps;
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/* SPD-defined CAS latencies */
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uint32_t caslat_X;
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uint32_t caslat_X_minus_1;
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uint32_t caslat_X_minus_2;
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uint32_t caslat_lowest_derated;
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/* basic timing parameters */
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uint32_t tRCD_ps;
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uint32_t tRP_ps;
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uint32_t tRAS_ps;
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uint32_t tWR_ps; /* maximum = 63750 ps */
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uint32_t tWTR_ps; /* maximum = 63750 ps */
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uint32_t tRFC_ps; /* max = 255 ns + 256 ns + .75 ns = 511750 ps */
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uint32_t tRRD_ps; /* maximum = 63750 ps */
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uint32_t tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
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uint32_t refresh_rate_ps;
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uint32_t extended_op_srt;
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uint32_t tIS_ps; /* byte 32, spd->ca_setup */
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uint32_t tIH_ps; /* byte 33, spd->ca_hold */
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uint32_t tDS_ps; /* byte 34, spd->data_setup */
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uint32_t tDH_ps; /* byte 35, spd->data_hold */
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uint32_t tRTP_ps; /* byte 38, spd->trtp */
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uint32_t tDQSQ_max_ps; /* byte 44, spd->tdqsq */
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uint32_t tQHS_ps; /* byte 45, spd->tqhs */
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uint32_t rcw[16];
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};
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#endif
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