280 lines
7.3 KiB
C
280 lines
7.3 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <notifier.h>
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#include <spi/spi.h>
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#include <mfd/mc13xxx.h>
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#include <io.h>
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#include <asm/mmu.h>
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#include <mach/imx5.h>
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#include <mach/imx-nand.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <mach/iomux-mx51.h>
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#include <mach/devices-imx51.h>
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#include <mach/iim.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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static iomux_v3_cfg_t f3s_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* FEC */
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MX51_PAD_EIM_EB2__FEC_MDIO,
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MX51_PAD_EIM_EB3__FEC_RDATA1,
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MX51_PAD_EIM_CS2__FEC_RDATA2,
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MX51_PAD_EIM_CS3__FEC_RDATA3,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_NANDF_RB2__FEC_COL,
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MX51_PAD_NANDF_RB3__FEC_RX_CLK,
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MX51_PAD_NANDF_CS2__FEC_TX_ER,
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MX51_PAD_NANDF_CS3__FEC_MDC,
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MX51_PAD_NANDF_CS4__FEC_TDATA1,
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MX51_PAD_NANDF_CS5__FEC_TDATA2,
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MX51_PAD_NANDF_CS6__FEC_TDATA3,
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MX51_PAD_NANDF_CS7__FEC_TX_EN,
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MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
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MX51_PAD_NANDF_D11__FEC_RX_DV,
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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MX51_PAD_NANDF_D8__FEC_TDATA0,
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MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_EIM_A20__GPIO2_14, /* LAN8700 reset pin */
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IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
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/* SD 1 */
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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MX51_PAD_SD1_DATA1__SD1_DATA1,
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MX51_PAD_SD1_DATA2__SD1_DATA2,
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MX51_PAD_SD1_DATA3__SD1_DATA3,
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/* SD 2 */
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MX51_PAD_SD2_CMD__SD2_CMD,
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MX51_PAD_SD2_CLK__SD2_CLK,
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MX51_PAD_SD2_DATA0__SD2_DATA0,
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MX51_PAD_SD2_DATA1__SD2_DATA1,
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MX51_PAD_SD2_DATA2__SD2_DATA2,
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MX51_PAD_SD2_DATA3__SD2_DATA3,
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/* CD/WP gpio */
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MX51_PAD_GPIO1_6__GPIO1_6,
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MX51_PAD_GPIO1_5__GPIO1_5,
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};
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static int babbage_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x90000000, 512 * 1024 * 1024);
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return 0;
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}
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mem_initcall(babbage_mem_init);
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#define BABBAGE_ECSPI1_CS0 (3 * 32 + 24)
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static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0};
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static struct spi_imx_master spi_0_data = {
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.chipselect = spi_0_cs,
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.num_chipselect = ARRAY_SIZE(spi_0_cs),
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};
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static const struct spi_board_info mx51_babbage_spi_board_info[] = {
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{
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.name = "mc13xxx-spi",
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.bus_num = 0,
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.chip_select = 0,
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},
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};
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#define MX51_CCM_CACRR 0x10
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static void babbage_power_init(void)
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{
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struct mc13xxx *mc13xxx;
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u32 val;
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mc13xxx = mc13xxx_get();
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if (!mc13xxx) {
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printf("could not get PMIC\n");
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return;
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}
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/* Write needed to Power Gate 2 register */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
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val &= ~0x10000;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
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/* Write needed to update Charger 0 */
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mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
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/* power up the system first */
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mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
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if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
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/* Set core voltage to 1.1V */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
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val &= ~0x1f;
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val |= 0x14;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
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val &= ~0x1f;
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val |= 0x1a;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
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val &= ~0x1f;
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val |= 0x1a;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
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} else {
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/* Setup VCC (SW2) to 1.225 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
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val &= ~0x1f;
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val |= 0x19;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.2 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
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val &= ~0x1f;
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val |= 0x18;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
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}
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if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) {
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/* Set switchers in PWM mode for Atlas 2.0 and lower */
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/* Setup the switcher mode for SW1 & SW2*/
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
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val &= ~0x3c0f;
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val |= 0x1405;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
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val &= ~0xf0f;
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val |= 0x505;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
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} else {
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/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
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/* Setup the switcher mode for SW1 & SW2*/
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
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val &= ~0x3c0f;
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val |= 0x2008;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
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val &= ~0xf0f;
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val |= 0x808;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
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}
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
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val &= ~0x34030;
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val |= 0x10020;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
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val &= ~0x1FC;
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val |= 0x1F4;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = 0x208;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
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udelay(200);
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#define GPIO_LAN8700_RESET (1 * 32 + 14)
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/* Reset the ethernet controller over GPIO */
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gpio_direction_output(GPIO_LAN8700_RESET, 0);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = 0x49249;
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mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
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udelay(500);
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gpio_set_value(GPIO_LAN8700_RESET, 1);
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}
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static int f3s_devices_init(void)
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{
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spi_register_board_info(mx51_babbage_spi_board_info,
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ARRAY_SIZE(mx51_babbage_spi_board_info));
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imx51_add_spi0(&spi_0_data);
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babbage_power_init();
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console_flush();
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imx51_init_lowlevel(800);
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clock_notifier_call_chain();
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imx51_iim_register_fec_ethaddr();
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imx51_add_fec(&fec_info);
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imx51_add_mmc0(NULL);
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imx51_add_mmc1(NULL);
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armlinux_set_bootparams((void *)0x90000100);
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armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
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return 0;
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}
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device_initcall(f3s_devices_init);
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static int f3s_part_init(void)
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{
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devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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late_initcall(f3s_part_init);
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static int f3s_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
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imx51_add_uart0();
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return 0;
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}
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console_initcall(f3s_console_init);
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