69 lines
2.0 KiB
C
69 lines
2.0 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/**
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* @file
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* @brief phyCORE-i.MX27 specific PLL setup
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*/
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#ifndef __PCM038_PLL_H
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#define __PCM038_PLL_H
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/* define the PLL setting we want to run the system */
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/* main clock divider settings immediately after reset (at 1.25 V core supply) */
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#define CSCR_VAL (CSCR_USB_DIV(3) | \
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CSCR_SD_CNT(3) | \
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CSCR_MSHC_SEL | \
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CSCR_H264_SEL | \
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CSCR_SSI1_SEL | \
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CSCR_SSI2_SEL | \
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CSCR_SP_SEL | /* 26 MHz reference */ \
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CSCR_MCU_SEL | /* 26 MHz reference */ \
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CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
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CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
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CSCR_FPM_EN | \
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CSCR_SPEN | \
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CSCR_MPEN)
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/* main clock divider settings after core voltage increases to 1.45 V */
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#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \
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CSCR_SD_CNT(3) | \
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CSCR_MSHC_SEL | \
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CSCR_H264_SEL | \
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CSCR_SSI1_SEL | \
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CSCR_SSI2_SEL | \
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CSCR_SP_SEL | /* 26 MHz reference */ \
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CSCR_MCU_SEL | /* 26 MHz reference */ \
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CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
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CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
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CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
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CSCR_FPM_EN | /* do not disable it! */ \
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CSCR_SPEN | \
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CSCR_MPEN)
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/* MPLL should provide a 399 MHz clock from the 26 MHz reference */
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#define MPCTL0_VAL (IMX_PLL_PD(0) | \
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IMX_PLL_MFD(51) | \
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IMX_PLL_MFI(7) | \
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IMX_PLL_MFN(35))
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/* SPLL should provide a 240 MHz clock from the 26 MHz reference */
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#define SPCTL0_VAL (IMX_PLL_PD(1) | \
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IMX_PLL_MFD(12) | \
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IMX_PLL_MFI(9) | \
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IMX_PLL_MFN(3))
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#endif /* __PCM038_PLL_H */
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