242 lines
8.8 KiB
C
242 lines
8.8 KiB
C
/*
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* This file contains the address info for various AM33XX modules.
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*
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* Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>,
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* Phytec Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_AM33XX_H
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#define __ASM_ARCH_AM33XX_H
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#include <sizes.h>
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/** AM335x Internal Bus Base addresses */
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#define AM33XX_L4_WKUP_BASE 0x44C00000
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#define AM33XX_L4_PER_BASE 0x48000000
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#define AM33XX_L4_FAST_BASE 0x4A000000
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/* the device numbering is the same as in the TRM memory map (SPRUH73G) */
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/* UART */
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#define AM33XX_UART0_BASE (AM33XX_L4_WKUP_BASE + 0x209000)
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#define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000)
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#define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000)
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/* GPIO */
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#define AM33XX_GPIO0_BASE (AM33XX_L4_WKUP_BASE + 0x207000 + 0x100)
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#define AM33XX_GPIO1_BASE (AM33XX_L4_PER_BASE + 0x4C000 + 0x100)
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#define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100)
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#define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100)
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/* EMFI Registers */
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#define AM33XX_EMFI0_BASE 0x4C000000
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#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
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#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
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/* I2C */
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#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000)
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#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000)
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#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000)
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/* GPMC */
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#define AM33XX_GPMC_BASE 0x50000000
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/* MMC */
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#define AM33XX_MMCHS0_BASE (AM33XX_L4_PER_BASE + 0x60000)
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#define AM33XX_MMC1_BASE (AM33XX_L4_PER_BASE + 0x1D8000)
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#define AM33XX_MMCHS2_BASE 0x47810000
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/* SPI */
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#define AM33XX_MCSPI0_BASE (AM33XX_L4_PER_BASE + 0x30000)
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#define AM33XX_MCSPI1_BASE (AM33XX_L4_PER_BASE + 0x1A0000)
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/* DTMTimer0 */
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#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
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/* PRM */
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#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
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#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00)
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#define AM33XX_PRM_RSTCTRL_RESET 0x1
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/* CTRL */
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#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000)
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#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600)
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/* Watchdog Timer */
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#define AM33XX_WDT_BASE 0x44E35000
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/* EMIF Base address */
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#define AM33XX_EMIF4_0_CFG_BASE 0x4C000000
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#define AM33XX_EMIF4_1_CFG_BASE 0x4D000000
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#define AM33XX_DMM_BASE 0x4E000000
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#define AM335X_CPSW_BASE 0x4A100000
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#define AM335X_CPSW_MDIO_BASE 0x4A101000
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/*DMM & EMIF4 MMR Declaration*/
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#define AM33XX_DMM_LISA_MAP__0 (AM33XX_DMM_BASE + 0x40)
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#define AM33XX_DMM_LISA_MAP__1 (AM33XX_DMM_BASE + 0x44)
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#define AM33XX_DMM_LISA_MAP__2 (AM33XX_DMM_BASE + 0x48)
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#define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C)
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#define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460)
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#define AM33XX_EMIF4_0_REG(REGNAME) (AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME)
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#define AM33XX_EMIF4_1_REG(REGNAME) (AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME)
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#define EMIF4_MOD_ID_REV 0x0
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#define EMIF4_SDRAM_STATUS 0x04
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#define EMIF4_SDRAM_CONFIG 0x08
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#define EMIF4_SDRAM_CONFIG2 0x0C
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#define EMIF4_SDRAM_REF_CTRL 0x10
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#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14
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#define EMIF4_SDRAM_TIM_1 0x18
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#define EMIF4_SDRAM_TIM_1_SHADOW 0x1C
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#define EMIF4_SDRAM_TIM_2 0x20
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#define EMIF4_SDRAM_TIM_2_SHADOW 0x24
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#define EMIF4_SDRAM_TIM_3 0x28
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#define EMIF4_SDRAM_TIM_3_SHADOW 0x2C
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#define EMIF0_SDRAM_MGMT_CTRL 0x38
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#define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C
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#define EMIF4_ZQ_CONFIG 0xC8
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#define EMIF4_DDR_PHY_CTRL_1 0xE4
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#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8
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#define EMIF4_DDR_PHY_CTRL_2 0xEC
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#define EMIF4_IODFT_TLGC 0x60
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#define AM33XX_VTP0_CTRL_REG 0x44E10E0C
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#define AM33XX_VTP1_CTRL_REG 0x48140E10
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/* OCMC */
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#define AM33XX_SRAM0_START 0x402f0400
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#define AM33XX_SRAM0_SIZE (SZ_128K - SZ_1K)
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#define AM33XX_SRAM_SCRATCH_SPACE 0x4030b800 /* start of public stack */
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#define AM33XX_SRAM_GPMC_STACK_SIZE (0x40)
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/* DDR offsets */
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#define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000
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#define AM33XX_DDR_IO_CTRL 0x44E10E04
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#define AM33XX_DDR_CKE_CTRL 0x44E1131C
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#define AM33XX_CONTROL_BASE_ADDR 0x44E10000
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#define AM33XX_DDR_CMD0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1404)
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#define AM33XX_DDR_CMD1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1408)
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#define AM33XX_DDR_CMD2_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x140C)
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#define AM33XX_DDR_DATA0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1440)
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#define AM33XX_DDR_DATA1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1444)
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#define AM33XX_CMD0_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x01C)
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#define AM33XX_CMD0_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x020)
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#define AM33XX_CMD0_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x024)
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#define AM33XX_CMD0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x028)
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#define AM33XX_CMD0_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x02C)
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#define AM33XX_CMD1_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x050)
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#define AM33XX_CMD1_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x054)
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#define AM33XX_CMD1_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x058)
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#define AM33XX_CMD1_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x05C)
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#define AM33XX_CMD1_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x060)
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#define AM33XX_CMD2_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x084)
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#define AM33XX_CMD2_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x088)
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#define AM33XX_CMD2_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x08C)
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#define AM33XX_CMD2_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x090)
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#define AM33XX_CMD2_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x094)
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#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0C8)
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#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0CC)
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#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0DC)
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#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0E0)
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#define AM33XX_DATA0_WRLVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F0)
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#define AM33XX_DATA0_WRLVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F4)
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#define AM33XX_DATA0_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F8)
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#define AM33XX_DATA0_GATELVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0FC)
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#define AM33XX_DATA0_GATELVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x100)
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#define AM33XX_DATA0_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x104)
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#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x108)
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#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x10C)
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#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x120)
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#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x124)
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#define AM33XX_DATA0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x138)
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#define AM33XX_DATA0_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x134)
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#define AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x16C)
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#define AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x180)
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#define AM33XX_DATA1_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x19C)
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#define AM33XX_DATA1_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1A8)
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#define AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1AC)
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#define AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1C4)
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#define AM33XX_DATA1_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1D8)
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/* Ethernet MAC ID from EFuse */
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#define AM33XX_MAC_ID0_LO (AM33XX_CTRL_BASE + 0x630)
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#define AM33XX_MAC_ID0_HI (AM33XX_CTRL_BASE + 0x634)
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#define AM33XX_MAC_ID1_LO (AM33XX_CTRL_BASE + 0x638)
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#define AM33XX_MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c)
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#define AM33XX_MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650)
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struct am33xx_cmd_control {
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u32 slave_ratio0;
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u32 dll_lock_diff0;
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u32 invert_clkout0;
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u32 slave_ratio1;
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u32 dll_lock_diff1;
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u32 invert_clkout1;
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u32 slave_ratio2;
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u32 dll_lock_diff2;
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u32 invert_clkout2;
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};
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struct am33xx_emif_regs {
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u32 emif_read_latency;
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u32 emif_tim1;
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u32 emif_tim2;
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u32 emif_tim3;
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u32 sdram_config;
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u32 sdram_config2;
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u32 zq_config;
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u32 sdram_ref_ctrl;
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};
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struct am33xx_ddr_data {
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u32 rd_slave_ratio0;
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u32 wr_dqs_slave_ratio0;
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u32 wrlvl_init_ratio0;
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u32 gatelvl_init_ratio0;
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u32 fifo_we_slave_ratio0;
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u32 wr_slave_ratio0;
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u32 use_rank0_delay;
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u32 dll_lock_diff0;
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};
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void am33xx_uart_soft_reset(void __iomem *uart_base);
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void am33xx_config_vtp(void);
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void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl);
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void am33xx_config_io_ctrl(int ioctrl);
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void am33xx_config_sdram(const struct am33xx_emif_regs *regs);
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void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr);
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void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
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const struct am33xx_emif_regs *emif_regs,
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const struct am33xx_ddr_data *ddr_data);
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#endif
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