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12 Commits

Author SHA1 Message Date
Sascha Hauer a570417687 ARM: am33xx: Pass uart_base to soft_reset function
To make am33xx_uart0_soft_reset more flexible rename it to
am33xx_uart_soft_reset and pass the UART base to it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 12:45:02 +02:00
Sascha Hauer ee7f5d5d50 ARM: OMAP: Safe boot info in fixed SRAM address
Storing the boot information in the image itself and passing a pointer
around between images is cumbersome and doesn't fit well with multiimage
support where the pointer we pass around is already occupied by the
devicetree.
Do the same as U-Boot does and store the boot information at the bottom
of the SRAM public stack.
To maintain the compatibility between new xloaders and older barebox
binaries we still pass the boot information to the next stage via pointer.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-12-10 14:35:34 +01:00
Jan Luebbe ed02d24564 ARM: am33xx: implement cpu revision decoding
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-08-27 07:12:33 +02:00
Teresa Gámez 9f122f8bf0 ARM: am33xx: Cleanup of lowlevel code
There is a lot of duplicate lowlevel code between the
am33xx boards. Move this code to am33xx_generic and
create structs for sdram settings.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-08-27 07:12:33 +02:00
Sascha Hauer 65504828dd ARM: omap: fix omap_save_bootinfo
omap_save_bootinfo derefences the argument passed to barebox without
checking it for validity. This breaks 2nd stage booting where r0
is undefined. The best we can do is to check whether the pointer is
somewhere in SRAM and is word aligned. This at least makes sure that
we do not oops. This introduces SoC specific xxx_save_bootinfo variants
since the SRAM addresses/sizes differ between SoCs.

Additionally fix the prototype for omap_save_bootinfo. It uses r0, so
it must be passed this variable.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-08-27 07:12:33 +02:00
Shravan kumar 692db70b61 PCM051: Add first stage support
This patch adds first stage support for PCM051.

Signed-off-by: Shravan kumar <shravan.k@phytec.in>
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-07-10 23:30:26 +02:00
Teresa Gámez 5e7c87a269 ARM: AM33xx: Add i2c support for AM33xx
Added device register functions and cpu_is_am33xx()
function.
Adapted the i2c-omap driver. AM335x has a lower
clock rate and the timeout of polling the isr function
had to be increased.

Based on a patch from Shravan Kumar <shravan.k@phytec.in>.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-06-21 08:05:54 +02:00
Jan Luebbe 3b16061615 arm: omap: am33xx: set up SPI devices
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-06-18 21:33:58 +02:00
Jan Luebbe f838be333e am33xx: add defines for GPIOs
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-04-19 07:25:46 +02:00
Jan Luebbe fa012d47e4 arm: beaglebone: add first-stage support for AM335x and board
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-12-20 12:30:26 +01:00
Teresa Gámez 024698e43a ARM AM33XX: Add MMC Bases
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-12-20 12:27:38 +01:00
Teresa Gámez 4746717a5d ARM OMAP AM33XX: create new ARCH for AM33xx
Created ARCH for AM33xx boards as second stage bootloader.
This includes:
- Added dmtimer0
- Created basic header files
- Added MMC support for ARCH_AM33XX
- Added reset function

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>

Some header file cleanup by:
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-12-20 11:43:10 +01:00