3ee217a69c
a) use the more CPU specific S3C* macro names b) move the register description out of the way, as more recent CPUs using a different layout and more features Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
165 lines
4.3 KiB
C
165 lines
4.3 KiB
C
/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/**
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* @file
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* @brief Basic clock, sdram and timer handling for S3C24xx CPUs
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*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/s3c-iomap.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-busctl.h>
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#include <mach/s3c24xx-gpio.h>
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/**
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* Calculate the amount of connected and available memory
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* @return Memory size in bytes
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*/
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uint32_t s3c24xx_get_memory_size(void)
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{
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uint32_t reg, size;
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/*
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* detect the current memory size
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*/
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reg = readl(S3C_BANKSIZE);
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switch (reg & 0x7) {
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case 0:
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size = SZ_32M;
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break;
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case 1:
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size = SZ_64M;
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break;
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case 2:
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size = SZ_128M;
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break;
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case 4:
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size = SZ_2M;
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break;
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case 5:
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size = SZ_4M;
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break;
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case 6:
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size = SZ_8M;
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break;
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default:
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size = SZ_16M;
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break;
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}
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/*
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* Is bank7 also configured for SDRAM usage?
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*/
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if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
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size <<= 1; /* also count this bank */
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return size;
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}
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void s3c24xx_disable_second_sdram_bank(void)
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{
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writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
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writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
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}
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#define S3C_WTCON (S3C_WATCHDOG_BASE)
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#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
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#define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08)
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void __noreturn reset_cpu(unsigned long addr)
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{
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/* Disable watchdog */
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writew(0x0000, S3C_WTCON);
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/* Initialize watchdog timer count register */
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writew(0x0001, S3C_WTCNT);
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/* Enable watchdog timer; assert reset at timer timeout */
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writew(0x0021, S3C_WTCON);
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/* loop forever and wait for reset to happen */
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while(1)
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;
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}
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EXPORT_SYMBOL(reset_cpu);
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/**
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@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
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@section s3c24xx_boards Boards using S3C24xx Processors
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@li @subpage arch/arm/boards/a9m2410/a9m2410.c
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@li @subpage arch/arm/boards/a9m2440/a9m2440.c
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@section s3c24xx_arch Documentation for S3C24xx Architectures Files
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@li @subpage arch/arm/mach-s3c24xx/generic.c
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@section s3c24xx_mem_map SDRAM Memory Map
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SDRAM starts at address 0x3000.0000 up to the available amount of connected
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SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
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up to 128MiB each).
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@subsection s3c24xx_mem_generic_map Generic Map
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- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
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- 0x0800.0000 Start of I/O space.
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- 0x3000.0000 Start of SDRAM area.
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- 0x3000.0100 Start of the TAG list area.
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- 0x3000.8000 Start of the linux kernel (physical address).
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- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
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- 0x4800.0000 Start of the internal I/O area
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@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
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All S3C24xx common headers are located here.
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@note Do not add board specific header files/information here.
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*/
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/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
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@par barebox Map
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The location of the @a barebox itself depends on the available amount of
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installed SDRAM memory:
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- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
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- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
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- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
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Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
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the available memory.
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@note The RAM based filesystem and the stack resides always below the
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@a barebox start address.
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@li @subpage dev_s3c24xx_wd_handling
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@li @subpage dev_s3c24xx_pll_handling
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@li @subpage dev_s3c24xx_sdram_handling
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@li @subpage dev_s3c24xx_nandboot_handling
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*/
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