119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
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* Copyright (C) 2013 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*
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*/
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#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <of.h>
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#include <mach/bbu.h>
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#include <fec.h>
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#include <linux/micrel_phy.h>
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#include <mach/iomux-mx6.h>
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#include <mach/imx6.h>
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#define ETH_PHY_RST IMX_GPIO_NR(3, 23)
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#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
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MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
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#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL))
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#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL)
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#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
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static void phyflex_err006282_workaround(void)
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{
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/*
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* Boards beginning with 1362.2 have the SD4_DAT3 pin connected
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* to the CMIC. If this pin isn't toggled within 10s the boards
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* reset. The pin is unconnected on older boards, so we do not
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* need a check for older boards before applying this fixup.
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*/
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
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mdelay(2);
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
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mdelay(2);
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gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
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if (cpu_is_mx6q())
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mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
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else if (cpu_is_mx6dl())
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mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
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gpio_direction_input(MX6_PHYFLEX_ERR006282);
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}
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static int eth_phy_reset(void)
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{
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gpio_request(ETH_PHY_RST, "phy reset");
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gpio_direction_output(ETH_PHY_RST, 0);
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mdelay(1);
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gpio_set_value(ETH_PHY_RST, 1);
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return 0;
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}
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static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
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{
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phy_write(dev, 0x0d, device);
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phy_write(dev, 0x0e, reg);
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phy_write(dev, 0x0d, (1 << 14) | device);
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phy_write(dev, 0x0e, val);
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}
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static int ksz9031rn_phy_fixup(struct phy_device *dev)
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{
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mmd_write_reg(dev, 2, 8, 0x039F);
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return 0;
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}
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static int phytec_pfla02_init(void)
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{
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if (!of_machine_is_compatible("phytec,imx6q-pfla02") &&
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!of_machine_is_compatible("phytec,imx6dl-pfla02") &&
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!of_machine_is_compatible("phytec,imx6s-pfla02"))
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return 0;
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phyflex_err006282_workaround();
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eth_phy_reset();
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phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
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ksz9031rn_phy_fixup);
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imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
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return 0;
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}
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device_initcall(phytec_pfla02_init);
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static int phytec_pfla02_core_init(void)
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{
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if (!of_machine_is_compatible("phytec,imx6x-pbab01"))
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return 0;
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imx6_init_lowlevel();
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return 0;
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}
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postcore_initcall(phytec_pfla02_core_init);
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