e190bcf14d
The corresponding code doesn't use the lr register (neither explicitly nor implicitly by the bl instruction), so there is no gain in using r2 here. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
59 lines
1.6 KiB
ArmAsm
59 lines
1.6 KiB
ArmAsm
#include <linux/linkage.h>
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#include <init.h>
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#include <asm/system.h>
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.section ".text_bare_init_","ax"
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ENTRY(arm_cpu_lowlevel_init)
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/* set the cpu to SVC32 mode, mask irq and fiq */
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mrs r12, cpsr
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bic r12, r12, #0x1f
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orr r12, r12, #0xd3
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msr cpsr, r12
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#if __LINUX_ARM_ARCH__ >= 6
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/*
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* ICIALLU: Invalidate all instruction caches to PoU,
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* includes flushing of branch predictors.
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* Even if the i-cache is off it might contain stale entries
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* that are better discarded before enabling the cache.
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* Architectually this is even possible after a cold reset.
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*/
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mcr p15, 0, r12, c7, c5, 0
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/* DSB, ensure completion of the invalidation */
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mcr p15, 0, r12, c7, c10, 4
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/*
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* ISB, ensure instruction fetch path is in sync.
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* Note that the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
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* edition (ARM DDI 0406C.c) doesn't define this instruction in the
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* ARMv6 part (D12.7.10). It only has: "Support of additional
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* operations is IMPLEMENTATION DEFINED".
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* But an earlier version of the ARMARM (ARM DDI 0100I) does define it
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* as "Flush prefetch buffer (PrefetchFlush)".
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*/
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mcr p15, 0, r12, c7, c5, 4
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#endif
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/* disable MMU stuff and data/unified caches */
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mrc p15, 0, r12, c1, c0, 0 /* SCTLR */
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bic r12, r12, #(CR_M | CR_C | CR_B)
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bic r12, r12, #(CR_S | CR_R | CR_V)
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/* enable instruction cache */
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orr r12, r12, #CR_I
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#if __LINUX_ARM_ARCH__ >= 6
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orr r12, r12, #CR_U
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bic r12, r12, #CR_A
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#else
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orr r12, r12, #CR_A
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#endif
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#ifdef __ARMEB__
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orr r12, r12, #CR_B
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#endif
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mcr p15, 0, r12, c1, c0, 0 /* SCTLR */
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mov pc, lr
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ENDPROC(arm_cpu_lowlevel_init)
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