11dcfd13b9
Based on the same commit in the Kernel: | commit 828b1716459d00b3d57d4309d25a8d1ea241116a | Author: Shawn Guo <shawn.guo@linaro.org> | Date: Thu Jul 11 13:58:36 2013 +0800 | | ARM: dts: imx: share pad macro names between imx6q and imx6dl | | The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board | design can work with either chip plugged into the socket, e.g. sabresd | and sabreauto boards. | | We currently define pin groups in imx6q.dtsi and imx6dl.dtsi | respectively because the pad macro names are different between two | chips. This brings a maintenance burden on having the same label point | to the same pin group defined in two places. | | The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs | pad macro names. Then the pin groups becomes completely common between | imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the | long term maintenance of imx6q/dt pin settings becomes easier. | | Unfortunately, the change brings some dramatic diff stat, but it's all | about DTS file, and the ultimate net diff stat is good. | | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
68 lines
1.7 KiB
Text
68 lines
1.7 KiB
Text
/*
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* Copyright 2013 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6dl-tqma6s.dtsi"
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#include "imx6qdl-mba6x.dtsi"
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/ {
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model = "TQ TQMA6S on MBa6x";
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compatible = "tq,mba6x", "tq,tqma6s", "fsl,imx6dl";
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chosen {
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linux,stdout-path = &uart2;
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};
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memory {
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reg = <0x10000000 0x20000000>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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gpiobuttons {
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pinctrl_gpiobuttons_1: gpiogrp-1 {
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fsl,pins = <
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
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MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
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>;
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};
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};
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hog {
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pinctrl_hog: hoggrp-1 {
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fsl,pins = <
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* usdhc2 CD */
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
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MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
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MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
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MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
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MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x80000000
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MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
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MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
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MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
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MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
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>;
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};
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};
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};
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&disp0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_disp0_ipu1>;
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crtcs = <&ipu1 0>;
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};
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