11dcfd13b9
Based on the same commit in the Kernel: | commit 828b1716459d00b3d57d4309d25a8d1ea241116a | Author: Shawn Guo <shawn.guo@linaro.org> | Date: Thu Jul 11 13:58:36 2013 +0800 | | ARM: dts: imx: share pad macro names between imx6q and imx6dl | | The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board | design can work with either chip plugged into the socket, e.g. sabresd | and sabreauto boards. | | We currently define pin groups in imx6q.dtsi and imx6dl.dtsi | respectively because the pad macro names are different between two | chips. This brings a maintenance burden on having the same label point | to the same pin group defined in two places. | | The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs | pad macro names. Then the pin groups becomes completely common between | imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the | long term maintenance of imx6q/dt pin settings becomes easier. | | Unfortunately, the change brings some dramatic diff stat, but it's all | about DTS file, and the ultimate net diff stat is good. | | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
100 lines
3 KiB
Text
100 lines
3 KiB
Text
/*
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* Copyright 2013 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx6dl.dtsi"
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#include "imx6qdl-tqma6x.dtsi"
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&iomuxc {
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can1 {
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pinctrl_can1_1: can1grp-1 {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
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MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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>;
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};
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};
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can2 {
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pinctrl_can2_1: can2grp-1 {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
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>;
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};
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};
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disp0 {
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pinctrl_disp0_ipu1: disp0grp-1 {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
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>;
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};
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};
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i2c3 {
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pinctrl_i2c3_2: i2c3grp-2 {
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fsl,pins = <
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MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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>;
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};
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};
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uart2 {
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pinctrl_uart2_2: uart2grp-2 {
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fsl,pins = <
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MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
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MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
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>;
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};
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};
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usdhc2 {
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pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x000070f0
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x000070f0
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
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>;
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};
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};
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};
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