11dcfd13b9
Based on the same commit in the Kernel: | commit 828b1716459d00b3d57d4309d25a8d1ea241116a | Author: Shawn Guo <shawn.guo@linaro.org> | Date: Thu Jul 11 13:58:36 2013 +0800 | | ARM: dts: imx: share pad macro names between imx6q and imx6dl | | The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board | design can work with either chip plugged into the socket, e.g. sabresd | and sabreauto boards. | | We currently define pin groups in imx6q.dtsi and imx6dl.dtsi | respectively because the pad macro names are different between two | chips. This brings a maintenance burden on having the same label point | to the same pin group defined in two places. | | The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs | pad macro names. Then the pin groups becomes completely common between | imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the | long term maintenance of imx6q/dt pin settings becomes easier. | | Unfortunately, the change brings some dramatic diff stat, but it's all | about DTS file, and the ultimate net diff stat is good. | | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
128 lines
2.3 KiB
Text
128 lines
2.3 KiB
Text
/*
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* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx6q.dtsi"
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/ {
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model = "Phytec phyFLEX-i.MX6 Ouad";
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compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
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memory {
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reg = <0x10000000 0x40000000>;
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};
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3_1>;
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status = "okay";
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio4 24 0>;
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flash: m25p80@0 {
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compatible = "m25p80";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
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MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
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>;
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};
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};
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pfla02 {
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pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
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fsl,pins = <
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
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MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
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>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet_3>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio3 23 0>;
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status = "disabled";
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};
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&flash {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0x80000>;
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};
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partition@1 {
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label = "barebox-environment";
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reg = <0x80000 0x10000>;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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nand-on-flash-bbt;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0x200000>;
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};
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partition@1 {
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label = "ubi";
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reg = <0x200000 0x3fe00000>;
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};
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};
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&ocotp1 {
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barebox,provide-mac-address = <&fec 0x620>;
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4_1>;
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status = "disabled";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_2>;
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cd-gpios = <&gpio1 4 0>;
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wp-gpios = <&gpio1 2 0>;
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status = "disabled";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3_2
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&pinctrl_usdhc3_pfla02>;
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cd-gpios = <&gpio1 27 0>;
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wp-gpios = <&gpio1 29 0>;
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status = "disabled";
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};
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