11dcfd13b9
Based on the same commit in the Kernel: | commit 828b1716459d00b3d57d4309d25a8d1ea241116a | Author: Shawn Guo <shawn.guo@linaro.org> | Date: Thu Jul 11 13:58:36 2013 +0800 | | ARM: dts: imx: share pad macro names between imx6q and imx6dl | | The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board | design can work with either chip plugged into the socket, e.g. sabresd | and sabreauto boards. | | We currently define pin groups in imx6q.dtsi and imx6dl.dtsi | respectively because the pad macro names are different between two | chips. This brings a maintenance burden on having the same label point | to the same pin group defined in two places. | | The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs | pad macro names. Then the pin groups becomes completely common between | imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the | long term maintenance of imx6q/dt pin settings becomes easier. | | Unfortunately, the change brings some dramatic diff stat, but it's all | about DTS file, and the ultimate net diff stat is good. | | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
44 lines
1 KiB
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44 lines
1 KiB
Text
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx6q.dtsi"
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#include "imx6qdl-sabresd.dtsi"
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/ {
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model = "Freescale i.MX6 Quad SABRE Smart Device Board";
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compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
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chosen {
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linux,stdout-path = "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000";
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
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MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
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MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
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MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
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MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
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MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
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>;
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};
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};
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};
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