Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Andrea GALLO <andrea.gallo@stericsson.com> Cc: Gael SALLES <gael.salles@stericsson.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
82 lines
2 KiB
C
82 lines
2 KiB
C
/*
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* linux/arch/arm/mach-nomadik/timer.c
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*
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* Copyright (C) 2008 STMicroelectronics
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* Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <asm/io.h>
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#include <mach/hardware.h>
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#include <mach/mtu.h>
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#include <mach/timex.h>
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/* Initial value for SRC control register: all timers use MXTAL/8 source */
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#define SRC_CR_INIT_MASK 0x00007fff
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#define SRC_CR_INIT_VAL 0x2aaa8000
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static u32 nmdk_cycle; /* write-once */
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static __iomem void *mtu_base;
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/*
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* clocksource: the MTU device is a decrementing counters, so we negate
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* the value being read.
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*/
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static uint64_t nmdk_read_timer(void)
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{
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return nmdk_cycle - readl(mtu_base + MTU_VAL(0));
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}
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static struct clocksource nmdk_clksrc = {
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.read = nmdk_read_timer,
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.shift = 20,
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.mask = 0xffffffff,
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};
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static void nmdk_timer_reset(void)
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{
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u32 cr;
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writel(0, mtu_base + MTU_CR(0)); /* off */
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/* configure load and background-load, and fire it up */
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writel(nmdk_cycle, mtu_base + MTU_LR(0));
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writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
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cr = MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
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writel(cr, mtu_base + MTU_CR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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}
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static int nmdk_timer_init(void)
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{
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u32 src_cr;
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unsigned long rate;
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rate = CLOCK_TICK_RATE; /* 2.4MHz */
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nmdk_cycle = (rate + 1000 / 2) / 1000;
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/* Configure timer sources in "system reset controller" ctrl reg */
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src_cr = readl(NOMADIK_SRC_BASE);
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src_cr &= SRC_CR_INIT_MASK;
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src_cr |= SRC_CR_INIT_VAL;
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writel(src_cr, NOMADIK_SRC_BASE);
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/* Save global pointer to mtu, used by functions above */
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mtu_base = (void *)NOMADIK_MTU0_BASE;
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/* Init the timer and register clocksource */
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nmdk_timer_reset();
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nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
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init_clock(&nmdk_clksrc);
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return 0;
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}
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core_initcall(nmdk_timer_init);
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