import dsp/fpga firmware and API headere version 2.4
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@ -180,19 +180,15 @@ typedef struct SuperFemto_ActivateRfReq
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uint8_t u8UsePdtchMsgq; ///< Set to '1' to use a separate MSGQUEUE for PDTCH primitives
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} msgq;
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// TRX RF clock options
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// RF options
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struct
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{
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int iClkCor; ///< Clock correction value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX, 7:Edge)
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} rfTrx;
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// RX RF clock options
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struct
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{
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int iClkCor; ///< Clock calibration value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved, 7:Edge)
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} rfRx;
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float fMaxTxPower; ///< Nominal maximum TX power in dBm
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uint8_t u8UseExtAtten; ///< Use the external attenuator to control TX power (0:No, 1:Yes)
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} rfTrx;
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} SuperFemto_ActivateRfReq_t;
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@ -313,20 +309,13 @@ typedef struct FemtoBts_RfClockSetupReq
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***************************************************************************/
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typedef struct SuperFemto_RfClockSetupReq
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{
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// TRX RF clock options
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// RF clock options
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struct
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{
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int iClkCor; ///< Clock correction value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX, 7:Edge)
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} rfTrx;
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// RX RF clock options
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struct
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{
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int iClkCor; ///< Clock calibration value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved, 7:Edge)
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} rfRx;
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// RF clock calibration
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struct {
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SuperFemto_ClkSrcId_t clkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:Edge, 8:NL)
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@ -385,20 +374,13 @@ typedef struct FemtoBts_RfClockInfoCnf
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***************************************************************************/
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typedef struct SuperFemto_RfClockInfoCnf
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{
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// TRX RF clock options
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// RF clock options
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struct
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{
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int iClkCor; ///< Clock correction value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX, 7:Edge)
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} rfTrx;
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// RX RF clock options
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struct
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{
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int iClkCor; ///< Clock calibration value in PPB.
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SuperFemto_ClkSrcId_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved, 7:Edge)
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} rfRx;
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// RF clock calibration
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struct {
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SuperFemto_ClkSrcId_t clkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:Edge, 8:NL)
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@ -470,8 +452,10 @@ typedef struct SuperFemto_GetTxCalibTblCnf
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GsmL1_Status_t status;
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GsmL1_FreqBand_t freqBand; ///< GSM Frequency band
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float fGain[80]; ///< Gain setting for output level from +50dBm to -29 dBm
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float fGainCorrVsArfcn[374]; /**< Gain correction (in dBm) for each ARFCN
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float fTxGainGmsk[80]; ///< Gain setting for GMSK output level from +50dBm to -29 dBm
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float fTx8PskCorr; ///< Gain adjustment for 8 PSK (default to +3.25 dB)
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float fTxExtAttCorr[31]; ///< Gain adjustment for external attenuator (0:@1dB, 1:@2dB, ..., 31:@32dB)
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float fTxRollOffCorr[374]; /**< Gain correction for each ARFCN
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for GSM-850 : 0=128, 1:129, ..., 123:251, [124-373]:unused
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for GSM-900 : 0=955, 1:956, ..., 70:1, ..., 317:956, [318-373]:unused
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for DCS-1800: 0=512, 1:513, ..., 373:885
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@ -493,8 +477,10 @@ typedef struct SuperFemto_SetTxCalibTblReq
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{
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GsmL1_FreqBand_t freqBand; ///< GSM Frequency band
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float fGain[80]; ///< Gain setting for output level from +50dBm to -29 dBm
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float fGainCorrVsArfcn[374]; /***< Gain correction (in dBm) for each ARFCN
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float fTxGainGmsk[80]; ///< Gain setting for GMSK output level from +50dBm to -29 dBm
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float fTx8PskCorr; ///< Gain adjustment for 8 PSK (default to +3.25 dB)
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float fTxExtAttCorr[31]; ///< Gain adjustment for external attenuator (0:@1dB, 1:@2dB, ..., 31:@32dB)
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float fTxRollOffCorr[374]; /**< Gain correction for each ARFCN
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for GSM-850 : 0=128, 1:129, ..., 123:251, [124-373]:unused
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for GSM-900 : 0=955, 1:956, ..., 70:1, ..., 317:956, [318-373]:unused
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for DCS-1800: 0=512, 1:513, ..., 373:885
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@ -549,11 +535,16 @@ typedef struct SuperFemto_GetRxCalibTblCnf
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GsmL1_FreqBand_t freqBand; ///< GSM Frequency band
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uint8_t bUplink; ///< Direction (0:Downlink, 1:Uplink)
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float fRssiCorrVsArfcn[374]; /***< RSSI correction (in dBm) for each ARFCN
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float fExtRxGain; ///< External RX gain
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float fRxMixGainCorr; ///< Mixer gain error compensation
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float fRxLnaGainCorr[3]; ///< LNA gain error compensation (1:@-12 dB, 2:@-24 dB, 3:@-36 dB)
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float fRxRollOffCorr[374]; /***< Frequency roll-off compensation
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for GSM-850 : 0=128, 1:129, ..., 123:251, [124-373]:unused
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for GSM-900 : 0=955, 1:956, ..., 70:1, ..., 317:956, [318-373]:unused
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for DCS-1800: 0=512, 1:513, ..., 373:885
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for PCS-1900: 0=512, 1:513, ..., 298:810, [299-373]:unused */
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uint8_t u8IqImbalMode; ///< IQ imbalance mode (0:off, 1:on, 2:auto)
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uint16_t u16IqImbalCorr[4]; ///< IQ imbalance compensation
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} SuperFemto_GetRxCalibTblCnf_t;
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/****************************************************************************
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@ -572,11 +563,16 @@ typedef struct SuperFemto_SetRxCalibTblReq
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GsmL1_FreqBand_t freqBand; ///< GSM Frequency band
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uint8_t bUplink; ///< Direction (0:Downlink, 1:Uplink)
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float fRssiCorrVsArfcn[374]; /***< RSSI correction (in dBm) for each ARFCN
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float fExtRxGain; ///< External RX gain
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float fRxMixGainCorr; ///< Mixer gain error compensation
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float fRxLnaGainCorr[3]; ///< LNA gain error compensation (1:@-12 dB, 2:@-24 dB, 3:@-36 dB)
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float fRxRollOffCorr[374]; /***< Frequency roll-off compensation
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for GSM-850 : 0=128, 1:129, ..., 123:251, [124-373]:unused
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for GSM-900 : 0=955, 1:956, ..., 70:1, ..., 317:956, [318-373]:unused
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for DCS-1800: 0=512, 1:513, ..., 373:885
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for PCS-1900: 0=512, 1:513, ..., 298:810, [299-373]:unused */
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uint8_t u8IqImbalMode; ///< IQ imbalance mode (0:off, 1:on, 2:auto)
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uint16_t u16IqImbalCorr[4]; ///< IQ imbalance compensation
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} SuperFemto_SetRxCalibTblReq_t;
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/****************************************************************************
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