gcc-4.6: Backport PR46934 fix
We have been hitting this issue on ARM/thumb and have a workaround in place to compile samba http://git.openembedded.org/openembedded/commit/recipes/samba/samba_3.2.15.bb?id=4ba7aa07c0dcd28f94515ff9927e2a04403fcf15 This backport should fix the gcc bug (From OE-Core rev: 75f7269a7a1da2494768d4be63c44b12c5cfeeeb) (From OE-Core rev: 446767c4c471b8ec932698a23af5a815d326a0be) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> Conflicts: meta/recipes-devtools/gcc/gcc-4.6.inc
This commit is contained in:
parent
70ff3b6d98
commit
8a20492e8a
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@ -1,6 +1,6 @@
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require gcc-common.inc
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PR = "r14"
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PR = "r15"
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# Third digit in PV should be incremented after a minor release
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# happens from this branch on gcc e.g. currently its 4.6.0
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@ -68,6 +68,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
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file://use-defaults.h-and-t-oe-in-B.patch \
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file://powerpc-e5500.patch \
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file://fix-for-ice-50099.patch \
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file://pr46934.patch \
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"
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SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch "
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@ -0,0 +1,392 @@
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2011-09-19 chengbin <bin.cheng@arm.com>
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Backport r174035 from mainline
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2011-05-22 Tom de Vries <tom@codesourcery.com>
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PR middle-end/48689
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* fold-const.c (fold_checksum_tree): Guard TREE_CHAIN use with
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CODE_CONTAINS_STRUCT (TS_COMMON).
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Backport r172297 from mainline
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2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
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Richard Earnshaw <rearnsha@arm.com>
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PR target/48250
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* config/arm/arm.c (arm_legitimize_reload_address): Update cases
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to use sign-magnitude offsets. Reject unsupported unaligned
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cases. Add detailed description in comments.
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* config/arm/arm.md (reload_outdf): Disable for ARM mode; change
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condition from TARGET_32BIT to TARGET_ARM.
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Backport r171978 from mainline
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2011-04-05 Tom de Vries <tom@codesourcery.com>
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PR target/43920
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* config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing
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for size.
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Backport r171632 from mainline
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2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
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* builtins.c (expand_builtin_memset_args): Use gen_int_mode
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instead of GEN_INT.
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Backport r171379 from mainline
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2011-03-23 Chung-Lin Tang <cltang@codesourcery.com>
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PR target/46934
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* config/arm/arm.md (casesi): Use the gen_int_mode() function
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to subtract lower bound instead of GEN_INT().
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Backport r171251 from mainline
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2011-03-21 Daniel Jacobowitz <dan@codesourcery.com>
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* config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
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for barrier handlers.
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Backport r171096 from mainline
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2011-03-17 Chung-Lin Tang <cltang@codesourcery.com>
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PR target/43872
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* config/arm/arm.c (arm_get_frame_offsets): Adjust early
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return condition with !cfun->calls_alloca.
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Index: gcc-4_6-branch/gcc/builtins.c
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===================================================================
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--- gcc-4_6-branch.orig/gcc/builtins.c 2011-10-17 17:45:32.050502963 -0700
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+++ gcc-4_6-branch/gcc/builtins.c 2011-10-17 17:46:11.154696878 -0700
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@@ -3972,6 +3972,7 @@
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{
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tree fndecl, fn;
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enum built_in_function fcode;
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+ enum machine_mode val_mode;
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char c;
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unsigned int dest_align;
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rtx dest_mem, dest_addr, len_rtx;
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@@ -4006,14 +4007,14 @@
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len_rtx = expand_normal (len);
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dest_mem = get_memory_rtx (dest, len);
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+ val_mode = TYPE_MODE (unsigned_char_type_node);
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if (TREE_CODE (val) != INTEGER_CST)
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{
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rtx val_rtx;
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val_rtx = expand_normal (val);
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- val_rtx = convert_to_mode (TYPE_MODE (unsigned_char_type_node),
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- val_rtx, 0);
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+ val_rtx = convert_to_mode (val_mode, val_rtx, 0);
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/* Assume that we can memset by pieces if we can store
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* the coefficients by pieces (in the required modes).
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@@ -4024,8 +4025,7 @@
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builtin_memset_read_str, &c, dest_align,
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true))
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{
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- val_rtx = force_reg (TYPE_MODE (unsigned_char_type_node),
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- val_rtx);
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+ val_rtx = force_reg (val_mode, val_rtx);
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store_by_pieces (dest_mem, tree_low_cst (len, 1),
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builtin_memset_gen_str, val_rtx, dest_align,
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true, 0);
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@@ -4051,7 +4051,8 @@
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true))
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store_by_pieces (dest_mem, tree_low_cst (len, 1),
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builtin_memset_read_str, &c, dest_align, true, 0);
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- else if (!set_storage_via_setmem (dest_mem, len_rtx, GEN_INT (c),
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+ else if (!set_storage_via_setmem (dest_mem, len_rtx,
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+ gen_int_mode (c, val_mode),
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dest_align, expected_align,
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expected_size))
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goto do_libcall;
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Index: gcc-4_6-branch/gcc/config/arm/arm.c
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===================================================================
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--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-10-17 17:45:41.914551883 -0700
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+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-10-17 17:48:35.447412371 -0700
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@@ -6406,23 +6406,126 @@
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HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
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HOST_WIDE_INT low, high;
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- if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
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- low = ((val & 0xf) ^ 0x8) - 0x8;
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- else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
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- /* Need to be careful, -256 is not a valid offset. */
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- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
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- else if (mode == SImode
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- || (mode == SFmode && TARGET_SOFT_FLOAT)
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- || ((mode == HImode || mode == QImode) && ! arm_arch4))
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- /* Need to be careful, -4096 is not a valid offset. */
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- low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
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- else if ((mode == HImode || mode == QImode) && arm_arch4)
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- /* Need to be careful, -256 is not a valid offset. */
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- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
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- else if (GET_MODE_CLASS (mode) == MODE_FLOAT
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- && TARGET_HARD_FLOAT && TARGET_FPA)
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- /* Need to be careful, -1024 is not a valid offset. */
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- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
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+ /* Detect coprocessor load/stores. */
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+ bool coproc_p = ((TARGET_HARD_FLOAT
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+ && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
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+ && (mode == SFmode || mode == DFmode
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+ || (mode == DImode && TARGET_MAVERICK)))
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+ || (TARGET_REALLY_IWMMXT
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+ && VALID_IWMMXT_REG_MODE (mode))
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+ || (TARGET_NEON
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+ && (VALID_NEON_DREG_MODE (mode)
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+ || VALID_NEON_QREG_MODE (mode))));
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+
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+ /* For some conditions, bail out when lower two bits are unaligned. */
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+ if ((val & 0x3) != 0
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+ /* Coprocessor load/store indexes are 8-bits + '00' appended. */
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+ && (coproc_p
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+ /* For DI, and DF under soft-float: */
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+ || ((mode == DImode || mode == DFmode)
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+ /* Without ldrd, we use stm/ldm, which does not
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+ fair well with unaligned bits. */
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+ && (! TARGET_LDRD
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+ /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
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+ || TARGET_THUMB2))))
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+ return false;
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+
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+ /* When breaking down a [reg+index] reload address into [(reg+high)+low],
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+ of which the (reg+high) gets turned into a reload add insn,
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+ we try to decompose the index into high/low values that can often
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+ also lead to better reload CSE.
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+ For example:
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+ ldr r0, [r2, #4100] // Offset too large
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+ ldr r1, [r2, #4104] // Offset too large
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+
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+ is best reloaded as:
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+ add t1, r2, #4096
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+ ldr r0, [t1, #4]
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+ add t2, r2, #4096
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+ ldr r1, [t2, #8]
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+
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+ which post-reload CSE can simplify in most cases to eliminate the
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+ second add instruction:
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+ add t1, r2, #4096
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+ ldr r0, [t1, #4]
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+ ldr r1, [t1, #8]
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+
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+ The idea here is that we want to split out the bits of the constant
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+ as a mask, rather than as subtracting the maximum offset that the
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+ respective type of load/store used can handle.
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+
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+ When encountering negative offsets, we can still utilize it even if
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+ the overall offset is positive; sometimes this may lead to an immediate
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+ that can be constructed with fewer instructions.
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+ For example:
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+ ldr r0, [r2, #0x3FFFFC]
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+
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+ This is best reloaded as:
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+ add t1, r2, #0x400000
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+ ldr r0, [t1, #-4]
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+
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+ The trick for spotting this for a load insn with N bits of offset
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+ (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
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+ negative offset that is going to make bit N and all the bits below
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+ it become zero in the remainder part.
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+
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+ The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
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+ to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
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+ used in most cases of ARM load/store instructions. */
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+
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+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
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+ (((VAL) & ((1 << (N)) - 1)) \
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+ ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
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+ : 0)
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+
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+ if (coproc_p)
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
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+ else if (GET_MODE_SIZE (mode) == 8)
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+ {
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+ if (TARGET_LDRD)
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+ low = (TARGET_THUMB2
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+ ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
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+ : SIGN_MAG_LOW_ADDR_BITS (val, 8));
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+ else
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+ /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
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+ to access doublewords. The supported load/store offsets are
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+ -8, -4, and 4, which we try to produce here. */
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+ low = ((val & 0xf) ^ 0x8) - 0x8;
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+ }
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+ else if (GET_MODE_SIZE (mode) < 8)
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+ {
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+ /* NEON element load/stores do not have an offset. */
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+ if (TARGET_NEON_FP16 && mode == HFmode)
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+ return false;
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+
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+ if (TARGET_THUMB2)
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+ {
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+ /* Thumb-2 has an asymmetrical index range of (-256,4096).
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+ Try the wider 12-bit range first, and re-try if the result
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+ is out of range. */
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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+ if (low < -255)
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
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+ }
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+ else
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+ {
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+ if (mode == HImode || mode == HFmode)
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+ {
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+ if (arm_arch4)
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
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+ else
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+ {
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+ /* The storehi/movhi_bytes fallbacks can use only
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+ [-4094,+4094] of the full ldrb/strb index range. */
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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+ if (low == 4095 || low == -4095)
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+ return false;
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+ }
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+ }
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+ else
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+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
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+ }
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+ }
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else
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return false;
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@@ -15415,7 +15518,10 @@
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offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
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/* A leaf function does not need any stack alignment if it has nothing
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on the stack. */
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- if (leaf && frame_size == 0)
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+ if (leaf && frame_size == 0
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+ /* However if it calls alloca(), we have a dynamically allocated
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+ block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
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+ && ! cfun->calls_alloca)
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{
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offsets->outgoing_args = offsets->soft_frame;
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offsets->locals_base = offsets->soft_frame;
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Index: gcc-4_6-branch/gcc/config/arm/arm.h
|
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===================================================================
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--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-10-17 17:45:41.910551858 -0700
|
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+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-10-17 17:48:35.447412371 -0700
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@@ -2041,7 +2041,8 @@
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/* Try to generate sequences that don't involve branches, we can then use
|
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conditional instructions */
|
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#define BRANCH_COST(speed_p, predictable_p) \
|
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- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
|
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+ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
|
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+ : (optimize > 0 ? 2 : 0))
|
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|
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/* Position Independent Code. */
|
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/* We decide which register to use based on the compilation options and
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Index: gcc-4_6-branch/gcc/config/arm/arm.md
|
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===================================================================
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--- gcc-4_6-branch.orig/gcc/config/arm/arm.md 2011-10-17 17:46:11.002696119 -0700
|
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+++ gcc-4_6-branch/gcc/config/arm/arm.md 2011-10-17 17:46:11.202697111 -0700
|
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@@ -6187,7 +6187,7 @@
|
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[(match_operand:DF 0 "arm_reload_memory_operand" "=o")
|
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(match_operand:DF 1 "s_register_operand" "r")
|
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(match_operand:SI 2 "s_register_operand" "=&r")]
|
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- "TARGET_32BIT"
|
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+ "TARGET_THUMB2"
|
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"
|
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{
|
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enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
|
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@@ -8359,7 +8359,8 @@
|
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rtx reg = gen_reg_rtx (SImode);
|
||||
|
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emit_insn (gen_addsi3 (reg, operands[0],
|
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- GEN_INT (-INTVAL (operands[1]))));
|
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+ gen_int_mode (-INTVAL (operands[1]),
|
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+ SImode)));
|
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operands[0] = reg;
|
||||
}
|
||||
|
||||
Index: gcc-4_6-branch/gcc/config/arm/unwind-arm.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/config/arm/unwind-arm.c 2011-10-17 17:45:41.390549278 -0700
|
||||
+++ gcc-4_6-branch/gcc/config/arm/unwind-arm.c 2011-10-17 17:46:11.000000000 -0700
|
||||
@@ -1196,8 +1196,6 @@
|
||||
ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
|
||||
|
||||
if (data[0] & uint32_highbit)
|
||||
- phase2_call_unexpected_after_unwind = 1;
|
||||
- else
|
||||
{
|
||||
data += rtti_count + 1;
|
||||
/* Setup for entry to the handler. */
|
||||
@@ -1207,6 +1205,8 @@
|
||||
_Unwind_SetGR (context, 0, (_uw) ucbp);
|
||||
return _URC_INSTALL_CONTEXT;
|
||||
}
|
||||
+ else
|
||||
+ phase2_call_unexpected_after_unwind = 1;
|
||||
}
|
||||
if (data[0] & uint32_highbit)
|
||||
data++;
|
||||
Index: gcc-4_6-branch/gcc/fold-const.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/fold-const.c 2011-10-17 17:45:32.050502963 -0700
|
||||
+++ gcc-4_6-branch/gcc/fold-const.c 2011-10-17 17:46:11.178696990 -0700
|
||||
@@ -13788,7 +13788,8 @@
|
||||
if (TREE_CODE_CLASS (code) != tcc_type
|
||||
&& TREE_CODE_CLASS (code) != tcc_declaration
|
||||
&& code != TREE_LIST
|
||||
- && code != SSA_NAME)
|
||||
+ && code != SSA_NAME
|
||||
+ && CODE_CONTAINS_STRUCT (code, TS_COMMON))
|
||||
fold_checksum_tree (TREE_CHAIN (expr), ctx, ht);
|
||||
switch (TREE_CODE_CLASS (code))
|
||||
{
|
||||
Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr40887.c 2011-06-24 08:13:47.000000000 -0700
|
||||
+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c 2011-10-17 17:46:11.182697014 -0700
|
||||
@@ -1,5 +1,6 @@
|
||||
/* { dg-options "-O2 -march=armv5te" } */
|
||||
/* { dg-final { scan-assembler "blx" } } */
|
||||
+/* { dg-prune-output "switch .* conflicts with" } */
|
||||
|
||||
int (*indirect_func)();
|
||||
|
||||
Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr42575.c 2011-06-24 08:13:47.000000000 -0700
|
||||
+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c 2011-10-17 17:46:11.182697014 -0700
|
||||
@@ -1,4 +1,4 @@
|
||||
-/* { dg-options "-O2 -march=armv7-a" } */
|
||||
+/* { dg-options "-O2" } */
|
||||
/* Make sure RA does good job allocating registers and avoids
|
||||
unnecessary moves. */
|
||||
/* { dg-final { scan-assembler-not "mov" } } */
|
||||
Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr43698.c 2011-06-24 08:13:47.000000000 -0700
|
||||
+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c 2011-10-17 17:46:11.182697014 -0700
|
||||
@@ -1,5 +1,5 @@
|
||||
/* { dg-do run } */
|
||||
-/* { dg-options "-Os -march=armv7-a" } */
|
||||
+/* { dg-options "-Os" } */
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr44788.c 2011-06-24 08:13:47.000000000 -0700
|
||||
+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c 2011-10-17 17:46:11.182697014 -0700
|
||||
@@ -1,6 +1,6 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target arm_thumb2_ok } */
|
||||
-/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
|
||||
+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -mfpu=vfp3 -mfloat-abi=softfp" } */
|
||||
|
||||
void joint_decode(float* mlt_buffer1, int t) {
|
||||
int i;
|
||||
Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c
|
||||
===================================================================
|
||||
--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/sync-1.c 2011-06-24 08:13:47.000000000 -0700
|
||||
+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c 2011-10-17 17:46:11.182697014 -0700
|
||||
@@ -1,5 +1,6 @@
|
||||
-/* { dg-do run } */
|
||||
-/* { dg-options "-O2 -march=armv7-a" } */
|
||||
+
|
||||
+/* { dg-do run { target sync_int_long } } */
|
||||
+/* { dg-options "-O2" } */
|
||||
|
||||
volatile int mem;
|
||||
|
Loading…
Reference in New Issue