2003-10-15 23:53:47 +00:00
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/*
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2010-02-10 09:32:43 +00:00
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* Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
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2003-10-15 23:53:47 +00:00
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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2008-08-31 21:33:26 +00:00
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#include <config.h>
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2003-10-15 23:53:47 +00:00
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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2008-10-30 21:51:33 +00:00
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#include <fsl_esdhc.h>
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2003-10-15 23:53:47 +00:00
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#include <asm/cache.h>
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2008-06-06 13:42:40 +00:00
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#include <asm/io.h>
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2010-06-17 16:37:25 +00:00
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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2010-09-28 22:20:33 +00:00
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#include <post.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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2003-10-15 23:53:47 +00:00
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2008-02-08 22:44:53 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2003-10-15 23:53:47 +00:00
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int checkcpu (void)
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{
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2004-06-09 00:34:46 +00:00
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sys_info_t sysinfo;
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uint pvr, svr;
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2005-07-25 19:05:07 +00:00
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uint fam;
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2004-06-09 00:34:46 +00:00
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uint ver;
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uint major, minor;
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2008-06-10 21:53:46 +00:00
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struct cpu_type *cpu;
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2008-10-19 00:35:49 +00:00
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char buf1[32], buf2[32];
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2010-04-13 16:07:57 +00:00
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#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
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2008-10-16 13:01:15 +00:00
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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2010-04-13 16:07:57 +00:00
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#endif /* CONFIG_FSL_CORENET */
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2010-02-10 09:32:43 +00:00
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#ifdef CONFIG_DDR_CLK_FREQ
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2008-09-27 06:40:57 +00:00
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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2009-03-19 07:46:19 +00:00
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#else
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#ifdef CONFIG_FSL_CORENET
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2010-02-10 09:32:43 +00:00
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u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
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>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
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2008-05-29 06:21:24 +00:00
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#else
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u32 ddr_ratio = 0;
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2010-02-10 09:32:43 +00:00
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#endif /* CONFIG_FSL_CORENET */
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2009-03-19 07:46:19 +00:00
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#endif /* CONFIG_DDR_CLK_FREQ */
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2009-01-15 16:58:35 +00:00
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int i;
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2004-06-09 00:34:46 +00:00
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svr = get_svr();
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major = SVR_MAJ(svr);
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2008-08-12 16:14:19 +00:00
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#ifdef CONFIG_MPC8536
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major &= 0x7; /* the msb of this nibble is a mfg code */
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#endif
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2004-06-09 00:34:46 +00:00
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minor = SVR_MIN(svr);
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2003-10-15 23:53:47 +00:00
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2009-07-31 06:38:14 +00:00
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if (cpu_numcores() > 1) {
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2009-09-03 14:12:40 +00:00
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#ifndef CONFIG_MP
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puts("Unicore software on multiprocessor system!!\n"
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"To enable mutlticore build define CONFIG_MP\n");
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#endif
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2010-08-09 23:39:57 +00:00
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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2009-07-31 06:38:14 +00:00
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printf("CPU%d: ", pic->whoami);
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} else {
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puts("CPU: ");
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}
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2008-02-06 07:19:40 +00:00
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2009-07-31 06:38:14 +00:00
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cpu = gd->cpu;
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2008-02-06 07:19:40 +00:00
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2009-09-02 08:05:21 +00:00
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puts(cpu->name);
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if (IS_E_PROCESSOR(svr))
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puts("E");
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2008-02-06 07:19:40 +00:00
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2004-06-09 00:34:46 +00:00
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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2005-03-15 22:56:53 +00:00
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pvr = get_pvr();
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2005-07-25 19:05:07 +00:00
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fam = PVR_FAM(pvr);
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2005-03-15 22:56:53 +00:00
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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printf("Core: ");
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2009-10-21 18:23:54 +00:00
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if (PVR_FAM(PVR_85xx)) {
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switch(PVR_MEM(pvr)) {
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case 0x1:
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case 0x2:
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puts("E500");
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break;
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case 0x3:
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puts("E500MC");
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break;
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case 0x4:
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puts("E5500");
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break;
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default:
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puts("Unknown");
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break;
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}
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} else {
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puts("Unknown");
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2005-03-15 22:56:53 +00:00
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}
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2008-10-23 06:47:38 +00:00
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2005-03-15 22:56:53 +00:00
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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2004-06-09 00:34:46 +00:00
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get_sys_info(&sysinfo);
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2009-02-04 15:35:57 +00:00
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puts("Clock Configuration:");
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2009-07-31 06:38:14 +00:00
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for (i = 0; i < cpu_numcores(); i++) {
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2009-02-18 23:41:08 +00:00
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if (!(i & 3))
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printf ("\n ");
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2009-01-15 16:58:35 +00:00
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printf("CPU%d:%-4s MHz, ",
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i,strmhz(buf1, sysinfo.freqProcessor[i]));
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2009-02-04 15:35:57 +00:00
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}
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printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
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2008-05-29 06:21:24 +00:00
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2009-03-19 07:46:19 +00:00
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#ifdef CONFIG_FSL_CORENET
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if (ddr_sync == 1) {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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} else {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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}
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#else
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2007-12-07 10:59:26 +00:00
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switch (ddr_ratio) {
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case 0x0:
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2008-10-19 00:35:49 +00:00
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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2007-12-07 10:59:26 +00:00
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break;
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case 0x7:
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2009-03-19 07:46:19 +00:00
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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2008-10-19 00:35:49 +00:00
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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2007-12-07 10:59:26 +00:00
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break;
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default:
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2009-03-19 07:46:19 +00:00
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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2008-10-19 00:35:49 +00:00
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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2007-12-07 10:59:26 +00:00
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break;
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}
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2009-03-19 07:46:19 +00:00
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#endif
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2004-06-09 00:34:46 +00:00
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2009-03-19 07:46:19 +00:00
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
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2009-03-19 07:46:19 +00:00
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} else {
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mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.
This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.
checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-03 23:16:37 +00:00
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freqLocalBus);
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2009-03-19 07:46:19 +00:00
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}
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2003-10-15 23:53:47 +00:00
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2008-02-06 07:19:40 +00:00
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#ifdef CONFIG_CPM2
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2008-10-19 00:35:49 +00:00
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printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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2008-02-06 07:19:40 +00:00
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#endif
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2004-06-09 00:34:46 +00:00
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2009-05-20 16:30:29 +00:00
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#ifdef CONFIG_QE
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printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
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#endif
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2009-03-19 07:46:19 +00:00
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#ifdef CONFIG_SYS_DPAA_FMAN
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for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
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2010-06-17 05:08:29 +00:00
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printf(" FMAN%d: %s MHz\n", i + 1,
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2009-03-19 07:46:19 +00:00
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strmhz(buf1, sysinfo.freqFMan[i]));
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
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#endif
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2005-03-15 22:56:53 +00:00
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puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
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2003-10-15 23:53:47 +00:00
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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2010-06-28 20:00:46 +00:00
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
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2003-10-15 23:53:47 +00:00
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{
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2009-09-08 18:46:46 +00:00
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/* Everything after the first generation of PQ3 parts has RSTCR */
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
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2008-05-08 12:17:08 +00:00
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unsigned long val, msr;
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2003-10-15 23:53:47 +00:00
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/*
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* Initiate hard reset in debug control register DBCR0
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2009-09-08 18:46:46 +00:00
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* Make sure MSR[DE] = 1. This only resets the core.
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2003-10-15 23:53:47 +00:00
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*/
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2008-05-08 12:17:08 +00:00
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msr = mfmsr ();
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msr |= MSR_DE;
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mtmsr (msr);
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val = mfspr(DBCR0);
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val |= 0x70000000;
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mtspr(DBCR0,val);
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2009-09-08 18:46:46 +00:00
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#else
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
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udelay(100);
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#endif
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2007-09-24 17:32:13 +00:00
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2003-10-15 23:53:47 +00:00
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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2009-09-17 06:52:37 +00:00
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#ifdef CONFIG_FSL_CORENET
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return (gd->bus_clk + 8) / 16;
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#else
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2008-02-08 22:44:53 +00:00
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return (gd->bus_clk + 4UL)/8UL;
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2009-09-17 06:52:37 +00:00
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#endif
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2003-10-15 23:53:47 +00:00
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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unsigned long val;
|
2007-04-23 06:44:44 +00:00
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val = mfspr(SPRN_TSR);
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val |= TSR_WIS;
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mtspr(SPRN_TSR, val);
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2003-10-15 23:53:47 +00:00
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}
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#endif /* CONFIG_WATCHDOG */
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2008-10-30 21:51:33 +00:00
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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|
|
{
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
|
|
return fsl_esdhc_mmc_init(bis);
|
|
|
|
#else
|
|
|
|
return 0;
|
|
|
|
#endif
|
|
|
|
}
|
2010-06-17 16:37:25 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Print out the state of various machine registers.
|
|
|
|
* Currently prints out LAWs, BR0/OR0, and TLBs
|
|
|
|
*/
|
|
|
|
void mpc85xx_reginfo(void)
|
|
|
|
{
|
|
|
|
print_tlbcam();
|
|
|
|
print_laws();
|
|
|
|
print_lbc_regs();
|
|
|
|
}
|
2010-09-28 22:20:33 +00:00
|
|
|
|
|
|
|
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
|
|
|
|
|
|
|
|
/* Board-specific functions defined in each board's ddr.c */
|
|
|
|
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
|
|
|
|
unsigned int ctrl_num);
|
|
|
|
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
|
|
|
|
phys_addr_t *rpn);
|
|
|
|
unsigned int
|
|
|
|
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
|
|
|
|
|
|
|
|
static void dump_spd_ddr_reg(void)
|
|
|
|
{
|
|
|
|
int i, j, k, m;
|
|
|
|
u8 *p_8;
|
|
|
|
u32 *p_32;
|
|
|
|
ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
|
|
|
|
generic_spd_eeprom_t
|
|
|
|
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
|
|
|
|
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
|
|
|
|
fsl_ddr_get_spd(spd[i], i);
|
|
|
|
|
|
|
|
puts("SPD data of all dimms (zero vaule is omitted)...\n");
|
|
|
|
puts("Byte (hex) ");
|
|
|
|
k = 1;
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
|
|
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
|
|
|
|
printf("Dimm%d ", k++);
|
|
|
|
}
|
|
|
|
puts("\n");
|
|
|
|
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
|
|
|
|
m = 0;
|
|
|
|
printf("%3d (0x%02x) ", k, k);
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
|
|
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
|
|
|
p_8 = (u8 *) &spd[i][j];
|
|
|
|
if (p_8[k]) {
|
|
|
|
printf("0x%02x ", p_8[k]);
|
|
|
|
m++;
|
|
|
|
} else
|
|
|
|
puts(" ");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (m)
|
|
|
|
puts("\n");
|
|
|
|
else
|
|
|
|
puts("\r");
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
|
|
switch (i) {
|
|
|
|
case 0:
|
|
|
|
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
|
|
|
break;
|
|
|
|
#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
|
|
|
|
case 1:
|
|
|
|
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
printf("%s unexpected controller number = %u\n",
|
|
|
|
__func__, i);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
printf("DDR registers dump for all controllers "
|
|
|
|
"(zero vaule is omitted)...\n");
|
|
|
|
puts("Offset (hex) ");
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
|
|
|
|
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
|
|
|
|
puts("\n");
|
|
|
|
for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
|
|
|
|
m = 0;
|
|
|
|
printf("%6d (0x%04x)", k * 4, k * 4);
|
|
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
|
|
p_32 = (u32 *) ddr[i];
|
|
|
|
if (p_32[k]) {
|
|
|
|
printf(" 0x%08x", p_32[k]);
|
|
|
|
m++;
|
|
|
|
} else
|
|
|
|
puts(" ");
|
|
|
|
}
|
|
|
|
if (m)
|
|
|
|
puts("\n");
|
|
|
|
else
|
|
|
|
puts("\r");
|
|
|
|
}
|
|
|
|
puts("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* invalid the TLBs for DDR and setup new ones to cover p_addr */
|
|
|
|
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
|
|
|
|
{
|
|
|
|
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
|
|
unsigned long epn;
|
|
|
|
u32 tsize, valid, ptr;
|
|
|
|
phys_addr_t rpn = 0;
|
|
|
|
int ddr_esel;
|
|
|
|
|
|
|
|
ptr = vstart;
|
|
|
|
|
|
|
|
while (ptr < (vstart + size)) {
|
|
|
|
ddr_esel = find_tlb_idx((void *)ptr, 1);
|
|
|
|
if (ddr_esel != -1) {
|
|
|
|
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
|
|
|
|
disable_tlb(ddr_esel);
|
|
|
|
}
|
|
|
|
ptr += TSIZE_TO_BYTES(tsize);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup new tlb to cover the physical address */
|
|
|
|
setup_ddr_tlbs_phys(p_addr, size>>20);
|
|
|
|
|
|
|
|
ptr = vstart;
|
|
|
|
ddr_esel = find_tlb_idx((void *)ptr, 1);
|
|
|
|
if (ddr_esel != -1) {
|
|
|
|
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
|
|
|
|
} else {
|
|
|
|
printf("TLB error in function %s\n", __func__);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* slide the testing window up to test another area
|
|
|
|
* for 32_bit system, the maximum testable memory is limited to
|
|
|
|
* CONFIG_MAX_MEM_MAPPED
|
|
|
|
*/
|
|
|
|
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
|
|
{
|
|
|
|
phys_addr_t test_cap, p_addr;
|
|
|
|
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
|
|
|
|
|
|
|
|
#if !defined(CONFIG_PHYS_64BIT) || \
|
|
|
|
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
|
|
|
|
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
|
|
|
|
test_cap = p_size;
|
|
|
|
#else
|
|
|
|
test_cap = gd->ram_size;
|
|
|
|
#endif
|
|
|
|
p_addr = (*vstart) + (*size) + (*phys_offset);
|
|
|
|
if (p_addr < test_cap - 1) {
|
|
|
|
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
|
|
|
|
if (reset_tlb(p_addr, p_size, phys_offset) == -1)
|
|
|
|
return -1;
|
|
|
|
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
|
|
*size = (u32) p_size;
|
|
|
|
printf("Testing 0x%08llx - 0x%08llx\n",
|
|
|
|
(u64)(*vstart) + (*phys_offset),
|
|
|
|
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
|
|
|
|
} else
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* initialization for testing area */
|
|
|
|
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
|
|
{
|
|
|
|
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
|
|
|
|
|
|
|
|
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
|
|
|
|
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
|
|
|
|
*phys_offset = 0;
|
|
|
|
|
|
|
|
#if !defined(CONFIG_PHYS_64BIT) || \
|
|
|
|
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
|
|
|
|
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
|
|
|
|
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
|
|
|
|
puts("Cannot test more than ");
|
|
|
|
print_size(CONFIG_MAX_MEM_MAPPED,
|
|
|
|
" without proper 36BIT support.\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
printf("Testing 0x%08llx - 0x%08llx\n",
|
|
|
|
(u64)(*vstart) + (*phys_offset),
|
|
|
|
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* invalid TLBs for DDR and remap as normal after testing */
|
|
|
|
int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
|
|
|
|
{
|
|
|
|
unsigned long epn;
|
|
|
|
u32 tsize, valid, ptr;
|
|
|
|
phys_addr_t rpn = 0;
|
|
|
|
int ddr_esel;
|
|
|
|
|
|
|
|
/* disable the TLBs for this testing */
|
|
|
|
ptr = *vstart;
|
|
|
|
|
|
|
|
while (ptr < (*vstart) + (*size)) {
|
|
|
|
ddr_esel = find_tlb_idx((void *)ptr, 1);
|
|
|
|
if (ddr_esel != -1) {
|
|
|
|
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
|
|
|
|
disable_tlb(ddr_esel);
|
|
|
|
}
|
|
|
|
ptr += TSIZE_TO_BYTES(tsize);
|
|
|
|
}
|
|
|
|
|
|
|
|
puts("Remap DDR ");
|
|
|
|
setup_ddr_tlbs(gd->ram_size>>20);
|
|
|
|
puts("\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void arch_memory_failure_handle(void)
|
|
|
|
{
|
|
|
|
dump_spd_ddr_reg();
|
|
|
|
}
|
|
|
|
#endif
|