2011-06-16 23:30:47 +00:00
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-06-16 23:30:47 +00:00
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*/
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#ifndef ARMV7_H
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#define ARMV7_H
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2011-07-21 13:10:04 +00:00
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/* Cortex-A9 revisions */
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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#define MIDR_CORTEX_A9_R1P2 0x411FC092
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#define MIDR_CORTEX_A9_R1P3 0x411FC093
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2011-07-21 13:29:23 +00:00
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#define MIDR_CORTEX_A9_R2P10 0x412FC09A
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2011-07-21 13:10:04 +00:00
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2011-11-15 14:49:55 +00:00
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/* Cortex-A15 revisions */
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#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
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2013-02-12 01:33:41 +00:00
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#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
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2011-11-15 14:49:55 +00:00
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ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-09-19 16:06:41 +00:00
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/* Cortex-A7 revisions */
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#define MIDR_CORTEX_A7_R0P0 0x410FC070
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#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
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/* ID_PFR1 feature fields */
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#define CPUID_ARM_SEC_SHIFT 4
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#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
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#define CPUID_ARM_VIRT_SHIFT 12
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#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
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#define CPUID_ARM_GENTIMER_SHIFT 16
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#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
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/* valid bits in CBAR register / PERIPHBASE value */
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#define CBAR_MASK 0xFFFF8000
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2011-06-16 23:30:47 +00:00
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/* CCSIDR */
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#define CCSIDR_LINE_SIZE_OFFSET 0
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#define CCSIDR_LINE_SIZE_MASK 0x7
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#define CCSIDR_ASSOCIATIVITY_OFFSET 3
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#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
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#define CCSIDR_NUM_SETS_OFFSET 13
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#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
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/*
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* Values for InD field in CSSELR
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* Selects the type of cache
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*/
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#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
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#define ARMV7_CSSELR_IND_INSTRUCTION 1
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/* Values for Ctype fields in CLIDR */
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#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
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#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
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#define ARMV7_CLIDR_CTYPE_UNIFIED 4
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2013-09-19 16:06:39 +00:00
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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2015-03-02 13:24:45 +00:00
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#include <asm/io.h>
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2016-05-12 11:14:41 +00:00
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#include <asm/barriers.h>
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2015-03-20 15:16:17 +00:00
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2015-02-20 07:57:13 +00:00
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/*
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* Workaround for ARM errata # 798870
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* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
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* stalled for 1024 cycles to verify that its hazard condition still exists.
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*/
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static inline void v7_enable_l2_hazard_detect(void)
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{
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uint32_t val;
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/* L2ACTLR[7]: Enable hazard detect timeout */
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asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
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val |= (1 << 7);
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asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
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}
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2015-02-20 07:57:14 +00:00
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/*
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* Workaround for ARM errata # 799270
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* Ensure that the L2 logic has been used within the previous 256 cycles
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* before modifying the ACTLR.SMP bit. This is required during boot before
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* MMU has been enabled, or during a specified reset or power down sequence.
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*/
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static inline void v7_enable_smp(uint32_t address)
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{
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uint32_t temp, val;
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/* Read auxiliary control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
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/* Enable SMP */
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val |= (1 << 6);
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/* Dummy read to assure L2 access */
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temp = readl(address);
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temp &= 0;
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val |= temp;
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/* Write auxiliary control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
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CP15DSB;
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CP15ISB;
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}
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2015-02-20 07:57:13 +00:00
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void v7_en_l2_hazard_detect(void);
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2011-06-16 23:30:47 +00:00
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void v7_outer_cache_enable(void);
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void v7_outer_cache_disable(void);
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void v7_outer_cache_flush_all(void);
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void v7_outer_cache_inval_all(void);
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void v7_outer_cache_flush_range(u32 start, u32 end);
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void v7_outer_cache_inval_range(u32 start, u32 end);
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2015-04-21 05:18:24 +00:00
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#ifdef CONFIG_ARMV7_NONSEC
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2013-09-19 16:06:42 +00:00
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2014-07-12 13:24:03 +00:00
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int armv7_init_nonsec(void);
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2015-04-21 05:18:32 +00:00
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int armv7_apply_memory_carveout(u64 *start, u64 *size);
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2014-12-21 09:45:11 +00:00
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bool armv7_boot_nonsec(void);
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2013-09-19 16:06:42 +00:00
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ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-09-19 16:06:41 +00:00
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/* defined in assembly file */
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unsigned int _nonsec_init(void);
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2014-07-12 13:24:03 +00:00
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void _do_nonsec_entry(void *target_pc, unsigned long r0,
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unsigned long r1, unsigned long r2);
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2013-09-19 16:06:44 +00:00
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void _smp_pen(void);
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2014-07-12 13:24:03 +00:00
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extern char __secure_start[];
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extern char __secure_end[];
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2016-06-19 04:38:36 +00:00
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extern char __secure_stack_start[];
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extern char __secure_stack_end[];
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2014-07-12 13:24:03 +00:00
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2015-04-21 05:18:24 +00:00
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#endif /* CONFIG_ARMV7_NONSEC */
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ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
2013-09-19 16:06:41 +00:00
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2015-03-09 22:11:59 +00:00
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void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
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u32 cpu_rev_comb, u32 cpu_variant,
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u32 cpu_rev);
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2015-03-09 22:12:00 +00:00
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void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
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u32 cpu_variant, u32 cpu_rev);
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2013-09-19 16:06:39 +00:00
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#endif /* ! __ASSEMBLY__ */
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2011-06-16 23:30:47 +00:00
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#endif
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