sysmobts: Increase FPGA turn-a-round time to help NAND
For the Toshiba NAND chip if both NAND (read) and FPGA CS the time to switch might not be enough. Wait longer as discussed by email.
This commit is contained in:
parent
cea9019e5b
commit
14b386f1dc
|
@ -38,7 +38,7 @@
|
||||||
#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
|
#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
|
||||||
#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
|
#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
|
||||||
#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
|
#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
|
||||||
#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
|
#define DAVINCI_A2CR_VAL8 (0x0063059D) /* EMIF-A CS3 value for FPGA. */
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue