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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

This commit is contained in:
Albert ARIBAUD 2013-10-02 08:10:36 +02:00
parent 12eba1b493 827512fb11
commit 5c8d5b6fc1
21 changed files with 629 additions and 31 deletions
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11
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -27,6 +27,7 @@
#include <miiphy.h>
#include <cpsw.h>
#include <asm/errno.h>
#include <linux/compiler.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
@ -137,6 +138,16 @@ int arch_misc_init(void)
}
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
*/
__weak void am33xx_spl_board_init(void)
{
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
static void rtc32k_enable(void)
{
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;

8
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
View File

@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
.cm_div_m2_dpll = CM_WKUP + 0xA0,
};
const struct dpll_params dpll_mpu = {
struct dpll_params dpll_mpu_opp100 = {
CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
const struct dpll_params dpll_core_opp100 = {
1000, OSC-1, -1, -1, 10, 8, 4};
const struct dpll_params dpll_mpu = {
MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
50, OSC-1, -1, -1, 1, 1, 1};
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};

57
arch/arm/cpu/armv7/am33xx/sys_info.c
View File

@ -17,6 +17,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
@ -119,3 +120,59 @@ int print_cpuinfo(void)
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#ifdef CONFIG_AM33XX
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
{
int sil_rev;
sil_rev = readl(&cdev->deviceid) >> 28;
if (sil_rev == 1)
/* PG 2.0, efuse may not be set. */
return MPUPLL_M_800;
else if (sil_rev >= 2) {
/* Check what the efuse says our max speed is. */
int efuse_arm_mpu_max_freq;
efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
case AM335X_ZCZ_1000:
return MPUPLL_M_1000;
case AM335X_ZCZ_800:
return MPUPLL_M_800;
case AM335X_ZCZ_720:
return MPUPLL_M_720;
case AM335X_ZCZ_600:
case AM335X_ZCE_600:
return MPUPLL_M_600;
case AM335X_ZCZ_300:
case AM335X_ZCE_300:
return MPUPLL_M_300;
}
}
/* PG 1.0 or otherwise unknown, use the PG1.0 max */
return MPUPLL_M_720;
}
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
{
/* For PG2.1 and later, we have one set of values. */
if (sil_rev >= 2) {
switch (frequency) {
case MPUPLL_M_1000:
return TPS65910_OP_REG_SEL_1_3_2_5;
case MPUPLL_M_800:
return TPS65910_OP_REG_SEL_1_2_6;
case MPUPLL_M_720:
return TPS65910_OP_REG_SEL_1_2_0;
case MPUPLL_M_600:
case MPUPLL_M_300:
return TPS65910_OP_REG_SEL_1_1_3;
}
}
/* Default to PG1.0/PG2.0 values. */
return TPS65910_OP_REG_SEL_1_1_3;
}
#endif

3
arch/arm/cpu/armv7/omap-common/boot-common.c
View File

@ -76,6 +76,9 @@ void spl_board_init(void)
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
}
int board_mmc_init(bd_t *bis)

7
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
val = optimize_vcore_voltage(&vcores->iva);
do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, (*prcm)->prm_sldo_core_setup);
writel(2, (*prcm)->prm_sldo_mpu_setup);
writel(2, (*prcm)->prm_sldo_mm_setup);
}
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)

12
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
.prm_sldo_core_setup = 0x4ae07bc4,
.prm_sldo_core_ctrl = 0x4ae07bc8,
.prm_sldo_mpu_setup = 0x4ae07bcc,
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
/* SCRM stuff, used by some boards */
.scrm_auxclk0 = 0x4ae0a310,
@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
.prm_sldo_core_setup = 0x4ae07cc4,
.prm_sldo_core_ctrl = 0x4ae07cc8,
.prm_sldo_mpu_setup = 0x4ae07ccc,
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
.prm_abbldo_mpu_setup = 0x4ae07cdc,
.prm_abbldo_mpu_ctrl = 0x4ae07ce0,

12
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
View File

@ -11,9 +11,17 @@
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
/* MAIN PLL Fdll supported frequencies */
#define MPUPLL_M_1000 1000
#define MPUPLL_M_800 800
#define MPUPLL_M_720 720
#define MPUPLL_M_600 600
#define MPUPLL_M_550 550
#define MPUPLL_M_300 300
/* MAIN PLL Fdll = 550 MHz, by default */
#ifndef CONFIG_SYS_MPUCLK
#define CONFIG_SYS_MPUCLK 550
#define CONFIG_SYS_MPUCLK MPUPLL_M_550
#endif
#define UART_RESET (0x1 << 1)
@ -21,5 +29,7 @@
#define UART_SMART_IDLE_EN (0x1 << 0x3)
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;
#endif /* endif _CLOCKS_AM33XX_H_ */

12
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -38,6 +38,16 @@
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
#define DEVICE_ID_MASK 0x1FFF
/* MPU max frequencies */
#define AM335X_ZCZ_300 0x1FEF
#define AM335X_ZCZ_600 0x1FAF
#define AM335X_ZCZ_720 0x1F2F
#define AM335X_ZCZ_800 0x1E2F
#define AM335X_ZCZ_1000 0x1C2F
#define AM335X_ZCE_300 0x1FDF
#define AM335X_ZCE_600 0x1F9F
/* This gives the status of the boot mode pins on the evm */
#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
@ -509,6 +519,8 @@ struct ctrl_dev {
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
unsigned int resv5[106];
unsigned int efuse_sma; /* offset 0x1FC */
};
/* gmii_sel register defines */

4
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -10,6 +10,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <asm/arch/cpu.h>
#define BOARD_REV_ID 0x0
@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
#ifdef CONFIG_NOR_BOOT
void enable_norboot_pin_mux(void);
#endif
void am33xx_spl_board_init(void);
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
#endif

6
arch/arm/include/asm/omap_common.h
View File

@ -310,12 +310,6 @@ struct prcm_regs {
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
u32 prm_sldo_core_setup;
u32 prm_sldo_core_ctrl;
u32 prm_sldo_mpu_setup;
u32 prm_sldo_mpu_ctrl;
u32 prm_sldo_mm_setup;
u32 prm_sldo_mm_ctrl;
u32 prm_abbldo_mpu_setup;
u32 prm_abbldo_mpu_ctrl;

146
board/ti/am335x/board.c
View File

@ -26,6 +26,8 @@
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@ -244,6 +246,150 @@ const struct dpll_params dpll_ddr_evm_sk = {
const struct dpll_params dpll_ddr_bone_black = {
400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct am335x_baseboard_id header;
int mpu_vdd;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
if (board_is_bone(&header) || board_is_bone_lt(&header)) {
/* BeagleBone PMIC Code */
int usb_cur_lim;
/*
* Only perform PMIC configurations if board rev > A1
* on Beaglebone White
*/
if (board_is_bone(&header) && !strncmp(header.version,
"00A1", 4))
return;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/*
* On Beaglebone White we need to ensure we have AC power
* before increasing the frequency.
*/
if (board_is_bone(&header)) {
uchar pmic_status_reg;
if (tps65217_reg_read(TPS65217_STATUS,
&pmic_status_reg))
return;
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
puts("No AC power, disabling frequency switch\n");
return;
}
}
/*
* Override what we have detected since we know if we have
* a Beaglebone Black it supports 1GHz.
*/
if (board_is_bone_lt(&header))
dpll_mpu_opp100.m = MPUPLL_M_1000;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_POWER_PATH,
usb_cur_lim,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
*/
if (board_is_bone(&header)) {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
int sil_rev;
/*
* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
* MPU frequencies we support we use a CORE voltage of
* 1.1375V. For MPU voltage we need to switch based on
* the frequency we are running at.
*/
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
return;
/*
* Depending on MPU clock and PG we will need a different
* VDD to drive at that speed.
*/
sil_rev = readl(&cdev->deviceid) >> 28;
mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
dpll_mpu_opp100.m);
/* Tell the TPS65910 to use i2c */
tps65910_set_i2c_control();
/* First update MPU voltage. */
if (tps65910_voltage_update(MPU, mpu_vdd))
return;
/* Second, update the CORE voltage. */
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
return;
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
}
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
struct am335x_baseboard_id header;

10
drivers/net/cpsw.c
View File

@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
static void cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
struct phy_device *phy = priv->phydev;
struct phy_device *phy;
u32 mac_control = 0;
phy = priv->phydev;
if (!phy)
return;
phy_startup(phy);
*link = phy->link;
@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
dev,
slave->data->phy_if);
if (!phydev)
return -1;
phydev->supported &= supported;
phydev->advertising = phydev->supported;

2
drivers/power/pmic/Makefile
View File

@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

109
drivers/power/pmic/pmic_tps65217.c Normal file
View File

@ -0,0 +1,109 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <power/tps65217.h>
/**
* tps65217_reg_read() - Generic function that can read a TPS65217 register
* @src_reg: Source register address
* @src_val: Address of destination variable
* @return: 0 for success, not 0 on failure.
*/
int tps65217_reg_read(uchar src_reg, uchar *src_val)
{
return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
}
/**
* tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
* register or bit field regardless of protection
* level.
*
* @prot_level: Register password protection. Use
* TPS65217_PROT_LEVEL_NONE,
* TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
* @dest_reg: Register address to write.
* @dest_val: Value to write.
* @mask: Bit mask (8 bits) to be applied. Function will only
* change bits that are set in the bit mask.
*
* @return: 0 for success, not 0 on failure, as per the i2c API
*/
int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask)
{
uchar read_val;
uchar xor_reg;
int ret;
/*
* If we are affecting only a bit field, read dest_reg and apply the
* mask
*/
if (mask != TPS65217_MASK_ALL_BITS) {
ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
if (ret)
return ret;
read_val &= (~mask);
read_val |= (dest_val & mask);
dest_val = read_val;
}
if (prot_level > 0) {
xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
&xor_reg, 1);
if (ret)
return ret;
}
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
if (ret)
return ret;
if (prot_level == TPS65217_PROT_LEVEL_2) {
ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
&xor_reg, 1);
if (ret)
return ret;
ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
if (ret)
return ret;
}
return 0;
}
/**
* tps65217_voltage_update() - Function to change a voltage level, as this
* is a multi-step process.
* @dc_cntrl_reg: DC voltage control register to change.
* @volt_sel: New value for the voltage register
* @return: 0 for success, not 0 on failure.
*/
int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
{
if ((dc_cntrl_reg != TPS65217_DEFDCDC1) &&
(dc_cntrl_reg != TPS65217_DEFDCDC2) &&
(dc_cntrl_reg != TPS65217_DEFDCDC3))
return 1;
/* set voltage level */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
TPS65217_MASK_ALL_BITS))
return 1;
/* set GO bit to initiate voltage transition */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW,
TPS65217_DCDC_GO, TPS65217_DCDC_GO))
return 1;
return 0;
}

83
drivers/power/pmic/pmic_tps65910.c Normal file
View File

@ -0,0 +1,83 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <power/tps65910.h>
/*
* tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
* interface.
* @return: 0 on success, not 0 on failure
*/
int tps65910_set_i2c_control(void)
{
int ret;
uchar buf;
/* VDD1/2 voltage selection register access by control i/f */
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
&buf, 1);
if (ret)
return ret;
buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
&buf, 1);
}
/*
* tps65910_voltage_update() - Voltage switching for MPU frequency switching.
* @module: mpu - 0, core - 1
* @vddx_op_vol_sel: vdd voltage to set
* @return: 0 on success, not 0 on failure
*/
int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
{
uchar buf;
unsigned int reg_offset;
int ret;
if (module == MPU)
reg_offset = TPS65910_VDD1_OP_REG;
else
reg_offset = TPS65910_VDD2_OP_REG;
/* Select VDDx OP */
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
if (ret)
return ret;
buf &= ~TPS65910_OP_REG_CMD_MASK;
ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
if (ret)
return ret;
/* Configure VDDx OP Voltage */
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
if (ret)
return ret;
buf &= ~TPS65910_OP_REG_SEL_MASK;
buf |= vddx_op_vol_sel;
ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
if (ret)
return ret;
ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
if (ret)
return ret;
if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
return 1;
return 0;
}

6
include/configs/am335x_evm.h
View File

@ -170,6 +170,7 @@
"run mmcboot;" \
"setenv mmcdev 1; " \
"setenv bootpart 1:2; " \
"setenv mmcroot /dev/mmcblk1p2 ro; " \
"run mmcboot;" \
"run nandboot;"
@ -189,8 +190,13 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
/* SPL */
#ifndef CONFIG_NOR_BOOT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* CPSW support */

8
include/configs/dra7xx_evm.h
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@ -14,7 +14,13 @@
#define CONFIG_DRA7XX
#define CONFIG_ENV_IS_NOWHERE /* For now. */
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_CMD_SAVEENV
#define CONSOLEDEV "ttyO0"
#define CONFIG_CONS_INDEX 1

1
include/configs/pcm051.h
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@ -201,6 +201,7 @@
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the

83
include/power/tps65217.h Normal file
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@ -0,0 +1,83 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* For more details, please see the TRM at http://www.ti.com/product/tps65217a
*/
#ifndef __POWER_TPS65217_H__
#define __POWER_TPS65217_H__
/* I2C chip address */
#define TPS65217_CHIP_PM 0x24
/* Registers */
enum {
TPS65217_CHIPID = 0x00,
TPS65217_POWER_PATH,
TPS65217_INTERRUPT,
TPS65217_CHGCONFIG0,
TPS65217_CHGCONFIG1,
TPS65217_CHGCONFIG2,
TPS65217_CHGCONFIG3,
TPS65217_WLEDCTRL1,
TPS65217_WLEDCTRL2,
TPS65217_MUXCTRL,
TPS65217_STATUS,
TPS65217_PASSWORD,
TPS65217_PGOOD,
TPS65217_DEFPG,
TPS65217_DEFDCDC1,
TPS65217_DEFDCDC2,
TPS65217_DEFDCDC3,
TPS65217_DEFSLEW,
TPS65217_DEFLDO1,
TPS65217_DEFLDO2,
TPS65217_DEFLS1,
TPS65217_DEFLS2,
TPS65217_ENABLE,
TPS65217_DEFUVLO,
TPS65217_SEQ1,
TPS65217_SEQ2,
TPS65217_SEQ3,
TPS65217_SEQ4,
TPS65217_SEQ5,
TPS65217_SEQ6,
TPS65217_PMIC_NUM_OF_REGS,
};
#define TPS65217_PROT_LEVEL_NONE 0x00
#define TPS65217_PROT_LEVEL_1 0x01
#define TPS65217_PROT_LEVEL_2 0x02
#define TPS65217_PASSWORD_LOCK_FOR_WRITE 0x00
#define TPS65217_PASSWORD_UNLOCK 0x7D
#define TPS65217_DCDC_GO 0x80
#define TPS65217_MASK_ALL_BITS 0xFF
#define TPS65217_USB_INPUT_CUR_LIMIT_MASK 0x03
#define TPS65217_USB_INPUT_CUR_LIMIT_100MA 0x00
#define TPS65217_USB_INPUT_CUR_LIMIT_500MA 0x01
#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA 0x02
#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA 0x03
#define TPS65217_DCDC_VOLT_SEL_1125MV 0x09
#define TPS65217_DCDC_VOLT_SEL_1275MV 0x0F
#define TPS65217_DCDC_VOLT_SEL_1325MV 0x11
#define TPS65217_LDO_MASK 0x1F
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
int tps65217_reg_read(uchar src_reg, uchar *src_val);
int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask);
int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
#endif /* __POWER_TPS65217_H__ */

77
include/power/tps65910.h Normal file
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@ -0,0 +1,77 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* For more details, please see the TRM at http://www.ti.com/product/tps65910
*/
#ifndef __POWER_TPS65910_H__
#define __POWER_TPS65910_H__
#define MPU 0
#define CORE 1
#define TPS65910_SR_I2C_ADDR 0x12
#define TPS65910_CTRL_I2C_ADDR 0x2D
/* PMIC Register offsets */
enum {
TPS65910_VDD1_REG = 0x21,
TPS65910_VDD1_OP_REG = 0x22,
TPS65910_VDD2_REG = 0x24,
TPS65910_VDD2_OP_REG = 0x25,
TPS65910_DEVCTRL_REG = 0x3F,
};
/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
#define TPS65910_VGAIN_SEL_MASK (0x3 << 6)
#define TPS65910_ILMAX_MASK (0x1 << 5)
#define TPS65910_TSTEP_MASK (0x7 << 2)
#define TPS65910_ST_MASK (0x3)
#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6)
#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6)
#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6)
#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6)
#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5)
#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5)
#define TPS65910_REG_TSTEP_ (0x0 << 2)
#define TPS65910_REG_TSTEP_12_5 (0x1 << 2)
#define TPS65910_REG_TSTEP_9_4 (0x2 << 2)
#define TPS65910_REG_TSTEP_7_5 (0x3 << 2)
#define TPS65910_REG_TSTEP_6_25 (0x4 << 2)
#define TPS65910_REG_TSTEP_4_7 (0x5 << 2)
#define TPS65910_REG_TSTEP_3_12 (0x6 << 2)
#define TPS65910_REG_TSTEP_2_5 (0x7 << 2)
#define TPS65910_REG_ST_OFF (0x0)
#define TPS65910_REG_ST_ON_HI_POW (0x1)
#define TPS65910_REG_ST_OFF_1 (0x2)
#define TPS65910_REG_ST_ON_LOW_POW (0x3)
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
#define TPS65910_OP_REG_SEL (0x7F)
#define TPS65910_OP_REG_CMD_MASK (0x1 << 7)
#define TPS65910_OP_REG_CMD_OP (0x0 << 7)
#define TPS65910_OP_REG_CMD_SR (0x1 << 7)
#define TPS65910_OP_REG_SEL_MASK (0x7F)
#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */
/* Device control register . (DEVCTRL_REG) */
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
int tps65910_set_i2c_control(void);
int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
#endif /* __POWER_TPS65910_H__ */

3
spl/Makefile
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@ -87,7 +87,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \
drivers/power/pmic/libpmic.o
LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o