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MIPS: Ensure cache ops complete in mips_cache_reset 

Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton 2016-09-21 11:18:59 +01:00 committed by Daniel Schwierzeck
parent d608254b0a
commit 639200f6a0
1 changed files with 2 additions and 0 deletions
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2
arch/mips/lib/cache_init.S
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@ -420,6 +420,8 @@ l2_unbypass:
#endif
return:
/* Ensure all cache operations complete before returning */
sync
jr ra
END(mips_cache_reset)