83xx: Use the proper sequence for updating IMMR.
This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -200,9 +200,23 @@ boot_cold: /* time t 3 */
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nop
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nop
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boot_warm: /* time t 5 */
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boot_warm: /* time t 5 */
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mfmsr r5 /* save msr contents */
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mfmsr r5 /* save msr contents */
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/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
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bl 1f
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1: mflr r7
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lis r3, CONFIG_SYS_IMMR@h
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lis r3, CONFIG_SYS_IMMR@h
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ori r3, r3, CONFIG_SYS_IMMR@l
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ori r3, r3, CONFIG_SYS_IMMR@l
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lwz r6, IMMRBAR(r4)
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isync
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stw r3, IMMRBAR(r4)
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stw r3, IMMRBAR(r4)
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lwz r6, 0(r7) /* Arbitrary external load */
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isync
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lwz r6, IMMRBAR(r3)
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isync
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/* Initialise the E300 processor core */
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/* Initialise the E300 processor core */
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/*------------------------------------------*/
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/*------------------------------------------*/
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@ -212,9 +226,7 @@ boot_warm: /* time t 5 */
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* is loaded. Wait for the rest before branching
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* is loaded. Wait for the rest before branching
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* to another flash page.
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* to another flash page.
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*/
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*/
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addi r7, r3, 0x50b0
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1: lwz r6, 0x50b0(r3)
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1: dcbi 0, r7
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lwz r6, 0(r7)
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andi. r6, r6, 1
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andi. r6, r6, 1
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beq 1b
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beq 1b
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#endif
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#endif
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