sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

powerpc/mpc8xxx: Add auto select bank interleaving mode 

Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2012-10-08 07:44:27 +00:00 committed by Andy Fleming
parent a1d558a20f
commit 89b7809568
2 changed files with 37 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
arch/powerpc/cpu/mpc8xxx/ddr/options.c
View File

@ -474,6 +474,34 @@ static const struct dynamic_odt odt_unknown[4] = {
}
};
#endif
/*
* Automatically seleect bank interleaving mode based on DIMMs
* in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
* This function only deal with one or two slots per controller.
*/
static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
{
#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
if (pdimm[0].n_ranks == 4)
return FSL_DDR_CS0_CS1_CS2_CS3;
else if (pdimm[0].n_ranks == 2)
return FSL_DDR_CS0_CS1;
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (pdimm[0].n_ranks == 4)
return FSL_DDR_CS0_CS1_CS2_CS3;
#endif
if (pdimm[0].n_ranks == 2) {
if (pdimm[1].n_ranks == 2)
return FSL_DDR_CS0_CS1_CS2_CS3;
else
return FSL_DDR_CS0_CS1;
}
#endif
return 0;
}
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
@ -908,6 +936,9 @@ done:
else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
"cs0_cs1_cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
"auto", buf))
popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
else
printf("hwconfig has unrecognized parameter for bank_intlv.\n");
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
@ -1075,7 +1106,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
if (j != k) {
if (j && (j != k)) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
pinfo->memctl_opts[i].memctl_interleaving = 0;
printf("Not all controllers have compatible "

5
doc/README.fsl-ddr
View File

@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
# bank(chip-select) interleaving (auto)
setenv hwconfig "fsl_ddr:bank_intlv=auto"
This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
on DIMMs.
Memory controller address hashing
==================================
If the DDR controller supports address hashing, it can be enabled by hwconfig.