imx25: Add new hardware registers
Signed-off-by: Thomas Diener <dietho@gmx.de>
This commit is contained in:
Thomas Diener
Stefano Babic
parent
98d2cffd23
commit
bf0adb861e
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@ -161,6 +161,126 @@ struct aips_regs {
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u32 mpr_0_7;
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u32 mpr_8_15;
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};
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/* LCD controller registers */
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struct lcdc_regs {
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u32 lssar; /* Screen Start Address */
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u32 lsr; /* Size */
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u32 lvpwr; /* Virtual Page Width */
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u32 lcpr; /* Cursor Position */
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u32 lcwhb; /* Cursor Width Height and Blink */
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u32 lccmr; /* Color Cursor Mapping */
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u32 lpcr; /* Panel Configuration */
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u32 lhcr; /* Horizontal Configuration */
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u32 lvcr; /* Vertical Configuration */
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u32 lpor; /* Panning Offset */
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u32 lscr; /* Sharp Configuration */
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u32 lpccr; /* PWM Contrast Control */
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u32 ldcr; /* DMA Control */
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u32 lrmcr; /* Refresh Mode Control */
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u32 licr; /* Interrupt Configuration */
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u32 lier; /* Interrupt Enable */
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u32 lisr; /* Interrupt Status */
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u32 res0[3];
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u32 lgwsar; /* Graphic Window Start Address */
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u32 lgwsr; /* Graphic Window Size */
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u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
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u32 lgwpor; /* Graphic Window Panning Offset */
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u32 lgwpr; /* Graphic Window Position */
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u32 lgwcr; /* Graphic Window Control */
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u32 lgwdcr; /* Graphic Window DMA Control */
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u32 res1[5];
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u32 lauscr; /* AUS Mode Control */
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u32 lausccr; /* AUS mode Cursor Control */
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u32 res2[31 + 64*7];
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u32 bglut; /* Background Lookup Table */
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u32 gwlut; /* Graphic Window Lookup Table */
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};
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/* Wireless External Interface Module Registers */
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struct weim_regs {
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u32 cscr0u; /* Chip Select 0 Upper Register */
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u32 cscr0l; /* Chip Select 0 Lower Register */
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u32 cscr0a; /* Chip Select 0 Addition Register */
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u32 pad0;
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u32 cscr1u; /* Chip Select 1 Upper Register */
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u32 cscr1l; /* Chip Select 1 Lower Register */
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u32 cscr1a; /* Chip Select 1 Addition Register */
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u32 pad1;
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u32 cscr2u; /* Chip Select 2 Upper Register */
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u32 cscr2l; /* Chip Select 2 Lower Register */
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u32 cscr2a; /* Chip Select 2 Addition Register */
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u32 pad2;
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u32 cscr3u; /* Chip Select 3 Upper Register */
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u32 cscr3l; /* Chip Select 3 Lower Register */
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u32 cscr3a; /* Chip Select 3 Addition Register */
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u32 pad3;
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u32 cscr4u; /* Chip Select 4 Upper Register */
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u32 cscr4l; /* Chip Select 4 Lower Register */
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u32 cscr4a; /* Chip Select 4 Addition Register */
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u32 pad4;
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u32 cscr5u; /* Chip Select 5 Upper Register */
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u32 cscr5l; /* Chip Select 5 Lower Register */
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u32 cscr5a; /* Chip Select 5 Addition Register */
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u32 pad5;
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u32 wcr; /* WEIM Configuration Register */
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};
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/* Multi-Master Memory Interface */
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struct m3if_regs {
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u32 ctl; /* Control Register */
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u32 wcfg0; /* Watermark Configuration Register 0 */
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u32 wcfg1; /* Watermark Configuration Register1 */
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u32 wcfg2; /* Watermark Configuration Register2 */
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u32 wcfg3; /* Watermark Configuration Register 3 */
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u32 wcfg4; /* Watermark Configuration Register 4 */
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u32 wcfg5; /* Watermark Configuration Register 5 */
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u32 wcfg6; /* Watermark Configuration Register 6 */
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u32 wcfg7; /* Watermark Configuration Register 7 */
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u32 wcsr; /* Watermark Control and Status Register */
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u32 scfg0; /* Snooping Configuration Register 0 */
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u32 scfg1; /* Snooping Configuration Register 1 */
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u32 scfg2; /* Snooping Configuration Register 2 */
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u32 ssr0; /* Snooping Status Register 0 */
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u32 ssr1; /* Snooping Status Register 1 */
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u32 res0;
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u32 mlwe0; /* Master Lock WEIM CS0 Register */
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u32 mlwe1; /* Master Lock WEIM CS1 Register */
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u32 mlwe2; /* Master Lock WEIM CS2 Register */
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u32 mlwe3; /* Master Lock WEIM CS3 Register */
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u32 mlwe4; /* Master Lock WEIM CS4 Register */
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u32 mlwe5; /* Master Lock WEIM CS5 Register */
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};
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/* Pulse width modulation */
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struct pwm_regs {
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u32 cr; /* Control Register */
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u32 sr; /* Status Register */
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u32 ir; /* Interrupt Register */
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u32 sar; /* Sample Register */
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u32 pr; /* Period Register */
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u32 cnr; /* Counter Register */
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};
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/* Enhanced Periodic Interrupt Timer */
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struct epit_regs {
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u32 cr; /* Control register */
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u32 sr; /* Status register */
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u32 lr; /* Load register */
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u32 cmpr; /* Compare register */
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u32 cnr; /* Counter register */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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u32 test;
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};
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#endif
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@ -289,6 +409,8 @@ struct aips_regs {
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#define CCM_PERCLK_MASK 0x3f
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#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
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#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
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#define CCM_CRDR_BT_UART_SRC_SHIFT 29
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#define CCM_CRDR_BT_UART_SRC_MASK 7
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/* ESDRAM Controller register bitfields */
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#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
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@ -345,12 +467,65 @@ struct aips_regs {
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#define WSR_UNLOCK1 0x5555
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#define WSR_UNLOCK2 0xAAAA
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/* MAX bits */
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#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
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/* M3IF bits */
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#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
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/* WEIM bits */
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/* 13 fields of the upper CS control register */
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#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
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cnc, wsc, ew, wws, edc) \
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((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
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(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
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(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
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/* 12 fields of the lower CS control register */
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#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
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csa, ebc, dsz, csn, psr, cre, wrap, csen) \
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((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
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(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
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(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
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/* 14 fields of the additional CS control register */
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#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
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wwu, age, cnc2, fce) \
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((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
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(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
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(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
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(age) << 2 | (cnc2) << 1 | (fce) << 0)
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/* Names used in GPIO driver */
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#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
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#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
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#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
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#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
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/*
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* CSPI register definitions
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*/
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#define MXC_CSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 4
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#define MXC_SPI_BASE_ADDRESSES \
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IMX_CSPI1_BASE, \
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IMX_CSPI2_BASE, \
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IMX_CSPI3_BASE
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_1_2 0x12
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