Commit Graph

34520 Commits

Author SHA1 Message Date
Simon Glass 3721208fa7 x86: Remove Graeme Russ from the git alias file
As requested, remove Graeme's email address.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-21 09:37:46 -05:00
Tom Rini 34059d8f50 Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga 2015-12-19 22:05:31 -05:00
Dinh Nguyen 48275c96ff arm: socfpga: fix trivial header preprocessor for socfpga_common.h
Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with
__CONFIG_SOCFPGA_COMMON_H__ as the file is now called socfpga_common.h

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:44:56 +01:00
Dinh Nguyen a1684b6105 arm: socfpga: fix up a questionable macro for SDMMC
Move the macro into the socfpga_dwmci_clksel().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]
2015-12-20 03:44:56 +01:00
Dinh Nguyen e5ad7d9889 arm: socfpga: remove building scan manager
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-12-20 03:44:56 +01:00
Dinh Nguyen ed77aeb575 arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:44:56 +01:00
Dinh Nguyen ccf5648e0e arm: socfpga: remove note to add CONFIG_USB_DWC2_REG_ADDR
Now that the USB DWC2 probing is done from OF, remove this note to add
CONFIG_USB_DWC2_REG_ADDR.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:52 +01:00
Marek Vasut dbd6fcfbe2 arm: socfpga: Drop the board boilerplate
Drop all the common board code, since it is not completely useless.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut 8e535af2e4 arm: socfpga: Introduce common board code
The SoCFPGA has reached a point where every single board code become
the same, since each and every single board is probed equally from OF.
Move the common board code into arch/arm/mach-socfpga/ .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut ea08234651 arm: socfpga: Switch CONFIG_HOSTNAME to CONFIG_SYS_BOARD
We already have the CONFIG_SYS_BOARD variable, which defines the name
of the board. The value in CONFIG_HOSTNAME is exactly the same and is
thus just a duplicity, so switch it to reuse CONFIG_SYS_BOARD .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut a5cad67735 arm: socfpga: Switch CONFIG_G_DNL_MANUFACTURER to CONFIG_SYS_VENDOR
We already have the CONFIG_SYS_VENDOR variable, which defines the
manufacturer of the board. The value in CONFIG_G_DNL_MANUFACTURER
is just a duplicity, so switch it to reuse CONFIG_SYS_VENDOR .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut 92232747bb arm: socfpga: sockit: Zap VIRTUAL_TARGET
There is no VT for this board, so remove this incorrect macro.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut ac5516dd30 arm: socfpga: de0_nano: Zap VIRTUAL_TARGET
There is no VT for this board, so remove this incorrect macro.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:51 +01:00
Marek Vasut b5a5d2bd96 arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:51 +01:00
Marek Vasut 225217da28 arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:51 +01:00
Marek Vasut 9368aa6a68 arm: socfpga: mcvevk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:51 +01:00
Marek Vasut 5b5226a8e6 arm: socfpga: de0_nano: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:50 +01:00
Marek Vasut c90ada94fb arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:50 +01:00
Marek Vasut 70311e69fa arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:50 +01:00
Marek Vasut ef4b01b2f7 arm: socfpga: Allow DWC2 UDC probing from OF
The USB gadget framework does not support DM yet, so add this bit
to let DWC2 UDC probe from OF on platforms which support it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2015-12-20 03:36:50 +01:00
Marek Vasut faed7ac8fa arm: socfpga: socrates: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:50 +01:00
Marek Vasut 1f5f187172 arm: socfpga: sockit: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:50 +01:00
Marek Vasut 5df93c5564 arm: socfpga: de0_nano: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:50 +01:00
Marek Vasut b5aaa03634 arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:49 +01:00
Marek Vasut 6b9cdb716f arm: socfpga: arria5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:49 +01:00
Marek Vasut 5d8546efa7 arm: socfpga: socrates: Add missing PHY skew config
Add missing KSZ9021 PHY skew configuration for the EBV socrates board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-20 03:36:49 +01:00
Marek Vasut 22854bda80 net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF
Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

V2: - Implement struct ksz90x1_reg_field to describe the skew register
      fields more accurately.
    - Fix RXDV/TXEN skew register default value and offset.
2015-12-20 03:36:49 +01:00
Thomas Chou 1c0e84ca82 altera_qspi: initialize instr.mtd in flash_erase
Initialize instr.mtd in flash_erase(). This fixes the system
hang issue when CONFIG_MTD_PARTITIONS is selected.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-12-19 09:51:19 +08:00
Thomas Chou 11b35d557b serial-howto: remove altera_jtag_uart and altera_uart from the list
Since both altera_jtag_uart and altera_uart are converted to driver
model, remove them from the list of drivers remaining to convert.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Chin Liang See <clsee@altera.com>
2015-12-19 09:51:19 +08:00
Thomas Chou 4909f0e16a nios2: display altera sysid at startup
Display altera sysid at startup, which was once removed during
the move.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-12-19 09:51:19 +08:00
Marek Vasut aeea8754ff nios2: Soup up the shell experience
Enable command auto completion and enable $version variable. This makes
working with U-Boot far more enjoyable.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-19 09:48:14 +08:00
Marek Vasut 455e8fde4d nios2: Enable support for fitImage
The uImage format is legacy for years now, enable support for the
fitImage format, which allows combining multiple files (kernel and
dtb) into a single file, offers better protection of the payload
and so on.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-19 09:48:14 +08:00
Marek Vasut bc3abe149f nios2: Preconfigure $loadaddr variable
Preset the $loadaddr environment variable to some sane default, let's
say half of the RAM. This variable is where the kernel is loaded using
all sorts of .*load commands, so it's convenient to have it set.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-19 09:48:14 +08:00
Marek Vasut 7ef051ec9e nios2: Up the monitor size to 512kiB
The monitor is growing much larger with various additions, like fitImage,
command line completion, UBI etc. Make the monitor area larger so these
features can be safely added.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-19 09:48:14 +08:00
Marek Vasut 2aee06a259 nios2: Calculate the env position from monitor size
Reorder the 10m50 and 3c120 config files such, that the environment
position can be calculated from the monitor size. The environment is
placed right after the monitor. This removes one more ad-hoc variable.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-12-19 09:48:13 +08:00
Tom Rini 4832e17787 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2015-12-18 07:28:24 -05:00
Michal Simek b5e9b9a9a1 microblaze: Do not handle watchdog and gpio in SPL
watchdog and gpio are not validated for SPL that's why do not use them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek 4280f50238 microblaze: Enable DM by default
Enable DM for the whole architecture.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek ef159abf99 microblaze: Enable OF_CONTROL by default
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek 4632b1ea20 microblaze: Remove support for LL_TEMAC
LL_TEMAC is available at big endian MB and it is not properly tested
that's why the patch removes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek 4de9bbdcc8 microblaze: Use malloc setting via Kconfig
Clean board specific file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-18 13:15:58 +01:00
Michal Simek 4fcd0b33c7 microblaze: Make room for malloc before ELF
Create space below u-boot binary for early malloc.
It means memory layout is stack grows down, space for early malloc,
u-boot code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek 94067580a5 dm: net: Fix DM for targets which use MANUAL_RELOC
All ethernet operation needs to be updated for architectures which
requires MANUAL_RELOC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek 7bccc75a2b net: gem: Add driver dependencies to PHYLIB
Clear driver dependecies via Kconfig. Remove PHYLIB dependency from
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Michal Simek c942810787 net: gem: Fix typo in Kconfig entry
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek 9d9211ac11 net: gem: Separate recv and free_pkt functions
Use core to call net_process_received_packet() instead of call inside
the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek da872d7c13 net: gem: Fix return value from recv
recv function should return 0 instead of frame_len not to
proceed the same packet again in core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Michal Simek bcdfef7a26 net: gem: Setup default phy address to -1
Undefined phy address is -1 not 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-18 13:15:58 +01:00
Nathan Rossi 7bbf825492 arm: zynq: Update ZYBO config options
Update the ZYBO device tree and enable config options that relate to the
added devices in the device tree.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:58 +01:00
Nathan Rossi 04a44d3671 spi: zynq_qspi: Add configuration to disable LQSPI feature
When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the
device.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-18 13:15:57 +01:00