All parts of the pinmux information must be in the first 4 KiB. In
order to avoid some rather ugly linker script changes to ensure a
specific data segment was early enough, go back to asm for these pinmux
changes.
Signed-off-by: Tom Rini <trini@ti.com>
This patch
- Adds pin-mux for x8 parallel NAND device (MT29F4G08AB) present on AM43xx_EVM
- As above NAND device has blocksize=256k, pagesize=4k, oobsize=224, so by
design ROM code expects SPL to be flashed using BCH16 ECC scheme. Hence
CONFIG_NAND_OMAP_ECCSCHEME = OMAP_ECC_BCH16_CODE_HW is enabled.
- Specifies MTD partition table which needs same as kernel DTS for AM43xx_EVM.
- Populates other CONFIG_xx parameters required for NAND Boot on AM43xx
Signed-off-by: Pekon Gupta <pekon@ti.com>
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the
read latency expected will be CL+3 as per tests from HW folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team to
come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this README
Signed-off-by: Pekon Gupta <pekon@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Tom Rini <trini@ti.com>
GPMC controller is common IP to interface with both NAND and NOR flash devices.
Also, it supports max 8 chip-selects, which can be independently connected to
any of the devices.
But ROM code expects the boot-device to be connected to only chip-select[0].
Thus to resolve conflict between NOR and NAND boot. This patch:
- combines NOR and NAND configs spread in board files to common gpmc_init()
- configures GPMC based on boot-mode selected for SPL boot.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified. This has been tested
on AM335x GP EVM and Beaglebone White.
[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <matt.porter@linaro.org>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Tom Rini <trini@ti.com>
On further review, this change isn't helpful as our test environment
will likely blow away this information as part of ensuring an otherwise
known development environment, so just let them load the correct device
tree as needed.
This reverts commit bf9a9b6889.
Signed-off-by: Tom Rini <trini@ti.com>
Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also correct the bit masking of mac id read from the efuse.
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also adding mii command support to am335x common config.
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adding DPLLs Multiplier and DIvider values for GP EVM
Following are the DPLL locking frequencies at OPP NOM
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 400MHz
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
Following are the DPLL locking frequencies at OPP NOM:
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 266MHz
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Until we have device tree overlay support or something similar we need to
pass profile-specific device trees to the kernel. Update the logic to
expose a profile_number variable and update findfdt to use
am335x-evm-profileN.dtb. This is a TI SDK specific change as the answer
for upstream is to work towards device tree overlays or a similar
concept.
Signed-off-by: Tom Rini <trini@ti.com>
Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Move the MAC creation from the USB init to an function
that is called on every boot. This will then populate the
usbethaddr mac that kernel driver can pick up from the
device tree blob.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Add the support for the dra7xx xhci usb host.
dra7xx does not contain an EHCI controller so the headers
can be removed from the board file.
The xHCI host on dra7xx is connected to a usb2 phy so need to
add support to enable those clocks.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Recent patches declares board_usb_init function prototype for a new
usb architecture.
Turning on the OMAP_XHCI defines cause a redefinition compiler failure.
So update the board_usb_init to the latest prototype.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
This commit unifies board-specific USB initialization implementations
under one symbol (usb_board_init), declaration of which is available in
usb.h.
New API allows selective initialization of USB controllers whenever needed.
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
omap1510inn is orphan and has been for years now.
Reove it and, as it was the only arm925t target,
also remove arm925t support.
Update doc/README.scrapyard accordingly.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework]
Signed-off-by: Tom Rini <trini@ti.com>
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Signed-off-by: Tom Rini <trini@ti.com>
As this is a reference platform, update the README to note which IP
blocks are required for use due to design choices of the reference
rather than required by the SoC itself.
Signed-off-by: Tom Rini <trini@ti.com>
Use CONFIG_MACH_TYPE generic macro to set the machine type
number in the common arm code instead of setting it in the
board code.
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com>
Set the usbethaddr based on the OMAP DIE_ID registers
which should be unique for each processor.
Then set this as the usb ethernet MAC address.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Add the USB ehci support for the OMAP5 uEVM.
Configure the uEVM mux data
Add the flags to build the appropriate modules
Add the usb call backs to initialize the EHCI controller
Signed-off-by: Dan Murphy <dmurphy@ti.com>