Move the initialization of the LAWs into C code and provide an API
to allow modification of LAWs after init.
Board code is responsible to provide a law_table and num_law_entries.
We should be able to use the same code on 86xx as well.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
With serial, NE2000, IDE support. Tested in big-endian mode.
Memory size hard-coded to 128M for now, so don't play with
the -m option.
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
MPC837xERDB board support includes:
* DDR2 330MHz hardcoded (soldered on the board)
* Local Bus NOR Flash
* I2C, UART and RTC
* eTSEC RGMII (TSEC0 - RTL8211B with MII;
* TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware
* load)
Signed-off-by: Kevin Lam <kevin.lam@freescale.com>
Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).
Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Convert the board/freescale/common/Makefile to use
CONFIG_* options to select which files to conditionally
compile into the board/freescale/common library rather
than conditionally compiling entire files.
Now handles::
CONFIG_FSL_PIXIS
CONFIG_FSL_DIU_FB
CONFIG_PQ_MDS_PIB
CONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Use driver/net/uli526x.c as MPC8610HPCD default Ethernet driver.
Remove unused ethernet CONFIG_ options.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
These changes were identified by HighSmith Bill ,Mazzyar and Joseph for
DDR configuration in u-boot code. Some are related to performance, some
affect stability and some correct few basic errors in the current
configuration.
The changes have been tested and found to give better memory latency
figures on MPC8313eRDB.LMBench figures prove it.
The changes are:
- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0
(this may improve performance for application with many read
or write to open pages).
- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to
001 (activating all the CS when only one is used may cause
unwanted noise on the system)
- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on
Tras=45ns)
- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.
- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to
comply with the 3 ODT clk requirements)
- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.
- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.
- DDR_SDRAM_MODE[AL]changed from 0 to 1.
- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.
- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.
- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.
The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git
The last commit on this tree was 6775c68683
Signed-off-by: Poonam Aggrwal-b10812 <b10812@freescale.com>
Cc: Bill HighSmith <Bill.Highsmith@freescale.com>
Cc: Razzaz Mazyar <MRazzaz@freescale.com>
Cc: Josep P J <PJ.Joseph@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The isdram command prints out decoded information the "serial presence
detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when
debugging memory configuration problems.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MPC8360ERDK board support patch is added before
the commit 2c5b48fc20
so, miss clean up it.
The patch clean up the miss cache config.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
SH7710/SH7712 of SH3 CPU are supported.
SH771X is called SH-Ether, and has the Ether controller in CPU.
The driver of Ether is not included in this patch.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch add the support of map_physmem() and unmap_physmem()
used with Common Flash Interface(CFI) driver.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The TK885D board uses a TQM885D module from TQ, this port adds an
own configuration file and adds a last_stage_init() method to
configure the two PHYs, depending on the phy_auto_nego environment
variable.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Reduce the AL from 2 to 1 clock to improve the performance.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
According to the latest user manual of MPC8315E,
1) The SVCOD of HRCWL is different than 837x
2) The SCCR has changes
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The SPCR about TSEC priority is wrong.
Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com>
Signed-off-by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
clean up the cache config from configs.h of board
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This is MPC8360E based board with:
- 256MB fixed SDRAM;
- 8MB Intel Strata NOR flash;
- StMICRO 64MiB NAND flash;
- two 10/100/1000 ethernet ports connected via Broadcom
BCM5481 PHYs;
- two 10/100 ethernet ports connected via National
DP83848 PHYs;
- one PCI and one miniPCI slots;
- four serial ports (two NS16550-compatible, two UCCs);
- four USB ports working through MPC8360E "FHCI" USB controller;
- Fujitsu MB86277 graphics controller;
- Analog to Digital Converter/Touchscreen controller, AD7843
connected to SPI.
Features not supported in this patch are:
- StMICRO 64MiB NAND flash (patch sent);
- MINT framebuffer initialization (patch is pending);
- Fetching production information from the EEPROM via I2C;
- FHCI USB;
- Two slow UCCs used as RS-485 UARTs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
the new libfdt code only updates eth0 if CONFIG_HAS_ETH0
is defined; add the define to the missing board configs.
Thanks to Emilian Medve for finding this.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
vxWorks expects in
TLB 0 a entry for the Machine Check interrupt
TLB 1 a entry for the RAM
TLB 2 a entry for the EBC
TLB 3 a entry for the boot flash
After changing the baudrate to 9600 I had no problems to boot the
vxWorks image as distributed by WindRiver (Revision 2.0/1 from
June 18, 2007)
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Define the layout of a binary blob that contains a QE firmware and instructions
on how to upload it. Add function qe_upload_firmware() to parse the blob and
perform the actual upload. Add command-line command "qe fw" to take a firmware
blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the
'firmware' device tree node if U-Boot has uploaded a firmware. Fully define
'struct rsp' in immap_qe.h to include the actual RISC Special Registers.
Signed-off-by: Timur Tabi <timur@freescale.com>
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.
Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry. Actually use the bit masks for these items
since they are only a single bit.
Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Grab the FSL Book-E MAS register macros from Linux. Also added
defines for page sizes up to 4TB and removed SHAREN since it doesnt
really exist.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add new function readline_into_buffer() that allows the
output of readline to be put into a pointer to char buffer.
This refactoring allows other functions besides the
main command loop to also use the same input mechanism.
Signed-off-by: James Yang <James.Yang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
This is an API for external (standalone) applications running on top of
U-Boot, and is meant to be more extensible and robust than the existing
jumptable mechanism. It is similar to UNIX syscall approach. See api/README
for more details.
Included is the demo application using this new framework (api_examples).
Please note this is still an experimental feature, and is turned off by
default.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Assumes the presence of the aliases node in the DTS to
locate the pci and serial nodes for fixups.
Use consistent fdtaddr and fdtfile in environment variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch adds a post configuration callback for Spartan2/3 FPGAs.
pre and post configuration callback are now optional and
not called when the function pointer is set to NULL.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.
See README for the new options:
CONFIG_FPGA,
CONFIG_FPGA_<vendor>,
CONFIG_FPGA_<family>
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch adds a 'cu' like serial terminal command to u-boot
using which you can access other serial ports from the system console.
OpenMoko uses this in their Neo1973 phones to get access to the GSM
Modem and GPS chip from the bootloader.
Signed-off-by: Harald Welte <laforge@openmoko.org>
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
The MPC5200 OHCI controller operates in big endian, so
CFG_OHCI_BE_CONTROLLER must be defined for it to work properly.
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Add CFG_NAND_QUIET_TEST option to disable error message when
no NAND chip is installed on PMC440 boards.
Disable a couple of config defines that are only used for NAND_U_BOOT.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch adds more documenting comments to libfdt.h. Specifically,
these document the read/write functions (not including fdt_open_into()
and fdt_pack(), for now).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This patch adds some more documenting comments to libfdt.h.
Specifically this documents all the write-in-place functions.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
fdt_find_and_setprop() is used by several 4xx boards and it's
missing in the appropriate header. This patch eliminates a
warning when building U-Boot for such boards.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Acked-by: Stefan Roese <sr@denx.de>
convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Make libfdt the default for the WRS SBC8349 board.
Parallel of commit 35cc4e4823
done for the other 83xx based boards. Also fix a typo in CONFIG_PCI.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
The MPC8360E MDS config defined:
CONFIG_OF_HAS_BD_T
CONFIG_OF_HAS_UBOOT_ENV
Which we don't use or ever needed. This seems like copy-paste feature creep.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x.
This change guarantees that the environment will be located on the
first flash sector after the U-Boot image.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
currently-defined 83xx boards. This change guarantees that the environment
will be located on the first flash sector after the U-Boot image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
Note: this patch changes the configuration of some GPIO registers:
Register Old Value New Value
--------------- ---------- ----------
DCR GPIO0_TCR 0x0000000F 0x0000F0CF
DCR GPIO0_TSRH 0x55005000 0x00000000
DCR GPIO1_TCR 0xC2000000 0xE2000000
DCR GPIO1_TSRL 0x0C000000 0x00200000
DCR GPIO1_ISR2L 0x00050000 0x00110000
Signed-off-by: Larry Johnson <lrj@acm.org>
This patch makes two additions to GPIO support:
First, it adds function gpio_read_in_bit() to read the a bit from the
GPIO Input Register (GPIOx_IR) in the same way that function
gpio_read_out_bit() reads a bit from the GPIO Output Register
(GPIOx_OR).
Second, it modifies function gpio_set_chip_configuration() to provide
an additional option for configuring the GPIO from the
"CFG_4xx_GPIO_TABLE".
According to the 440EPx User's Manual, when an alternate output is used,
the three-state control is configured in one of two ways, depending on
the particular output. The first option is to select the corresponding
alternate three-state control in the GPIOx_TRSH/L registers. The second
option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
the GPIOx_TRSH/L registers, and set the corresponding bit in the
GPIOx_TCR register to enable the output. For example, the Manual
specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
the alternate three-state control (first option), and specifies
configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
enabled in the GPIOx_TCR register (second option).
Currently, gpio_set_chip_configuration() configures all alternate signal
outputs to use the first option. This patch allow the second option to
be selected by setting the "out_val" element in the table entry to
"GPIO_OUT_1". The first option is used when the "out_val" element is
set to "GPIO_OUT_0". Because "out_val" is not currently used when an
alternate signal is selected, and because all current GPIO tables set
"out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
not change any existing configurations.
Signed-off-by: Larry Johnson <lrj@acm.org>
The purpose of this routine is receiving a single network frame, outside of
U-Boot's NetLoop(). Exporting it to standalone programs that run on top of
U-Boot will let them utilise networking facilities. For sending a raw frame
the already existing eth_send() can be used.
The direct consumer of this routine is the newly introduced API layer for
external applications (enabled with CONFIG_API).
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Assumes the presence of the aliases node in the DTS to
locate the ethernet, pci and serial nodes for fixups.
Use consistent fdtaddr and fdtfile in environment variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch brings the PMC440 board configuration file.
Finally it enables the PMC440 board support.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This board never left prototyping state and it
became a millstone round my neck. So remove it.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch adds the Denali SDRAM controller definitions to "ppc440.h".
It also fixes two typos in the definitions, so the board-specific
"sdram.h" files containing these definitions are also fixed to avoid
compiler warnings.
Signed-off-by: Larry Johnson <lrj@acm.org>
On Sequoia & LWMON5 the virtual address of the POST cache test is now
moved to a bigger address. This enables usage of more memory on those
boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is
without using the absolute path to the cpu node. This makes it possible
to use this U-Boot version with both versions of cpu-node naming
"cpu@0" and the former "PowerPC,440EPx@0".
Signed-off-by: Stefan Roese <sr@denx.de>
When using dhcp/bootp the "netmask" environment variable is not
set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is
desireable, so the following patch adds this this option to the board
config.
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch update the 4xx fdt support. It enabled fdt booting
on the AMCC Kilauea and Sequoia for now. More can follow later
quite easily.
Signed-off-by: Stefan Roese <sr@denx.de>
CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
On the TQM885D the measurement of cpuclk with the PIT reference
timer ist not necessary. Since all module variants use the same
external 10 MHz oscillator, the cpuclk only depends on the PLL
configuration - which is readable by software.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 128. This result
in a refresh rate of 4 * 7.8 us at the default clock
66 MHz. At 133 MHz the value will be then 4 * 3.8 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Add a chip-features file providing definitions of the form
AT32AP700x_CHIP_HAS_<peripheral>
to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
map_physmem() returns a virtual address which can be used to access a
given physical address without involving the cache. unmap_physmem()
should be called when the virtual address returned by map_physmem() is
no longer needed.
This patch adds a stub implementation which simply returns the
physical address cast to a uchar * for all architectures except AVR32,
which converts the physical address to an uncached virtual mapping.
unmap_physmem() is a no-op on all architectures, but if any
architecture needs to do such mappings through the TLB, this is the
hook where those TLB entries can be invalidated.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This adds implementations of __raw_read[bwl] and __raw_write[bwl] to
m68k, ppc, nios and nios2. The m68k and ppc implementations were taken
from Linux.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones. Also, added some missing defines for
PCIE targets.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the MPC85xx CDS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the MPC8540 ADS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the MPC8560 ADS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
* Removed some misc environment setup
* Moved to using fdtfile & fdtaddr as fdt env var names
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the MPC8544DS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch selects the USB data pins in the 405EX GPIO and MFC (multi
function control) registers. This is done for the AMCC Kilauea and
Makalu eval boards.
Signed-off-by: Stefan Roese <sr@denx.de>
The following patch adds support for non-CFI flash ROMS, by hooking into the
CFI flash code and using most of its code, as recently discussed here in the
thread "Mixing CFI and non-CFI flashs".
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
setting the FIXD bit in the SDR0_MFR register. Here a description of the
symptoms:
Problem Description
------------------------------
If a DMA is performed between memory and PCI with the DMA 1 Controller
using prefetch, and as a result uses a special purpose buffer selected by
the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
the first part of the transfer sequence is performed twice. The
PPC440SPe PCI Controller requests more data than was needed such that in
the case of enforce memory protection, a host CPU exception can occur.
No data is corrupted, because data transfer is stopped in the PCI
Controller. Prefetch enable is specified by setting DMA Configuration
Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.
Behavior that may be observed in a running system
---------------------------------------------------------------------------
1. DMA performance is decreased because of the double access on the PCI bus
interface.
2. If an illegal access to some address on the PCI bus is detected at the
system level, a machine check or similar system error may occur.
Workarounds Available
----------------------------------
1. Do not program prefetch. Note that a prefetch command cannot be programmed
without selecting a special purpose buffer.
2. To avoid crossing a physical boundary of the PCI slave device, add 512
bytes of address to the PCI address range.
This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
from AMCC and slighly changed.
Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
After an error in the AMCC 405EX users manual now correctly configure
IRQ2 (Kilauea)/IRQ0 (Makalu) as alternate 2 signal for external IRQ
usage.
Signed-off-by: Stefan Roese <sr@denx.de>
Added the following fdt fixup helpers:
* do_fixup_by_prop{_u32} - Find matching nodes by property name/value
* do_fixup_by_compat{_u32} - Find matching nodes by compat
The _u32 variants work the same only the property they are setting
is know to be a 32-bit integer instead of a byte buffer.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from
the device tree compiler (dtc) project.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the generic fixup handling code out of cpu/mpc5xxx and cpu/mpc8260
into common/fdt_support.c and renamed:
do_fixup() -> do_fixup_by_path()
do_fixup_u32() -> do_fixup_by_path_u32()
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Removed:
fdt_node_is_compatible
fdt_find_node_by_type
fdt_find_compatible_node
To ease merge of newer libfdt as we aren't using them anywhere at this time.
Also moved fdt_find_and_setprop out of libfdt into fdt_support.c for the same
reason.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ugh. I *hate* to back this change out, but these compiler flags don't
work for relocation on all versions of GCC. I've not been able to
reproduce the environment in my setup (and hence, not been able to
find a combination that *does* work), so I've got no choice but to go
back to the old gcc flags and linker script.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This patch has been sent on:
- 29 Sep 2007
Although mips_io_port_base is currently a part of IDE command, it is quite
fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move
it to MIPS general part, and introduce `set_io_port_base()' from Linux.
This patch is triggered by multiple definition of `mips_io_port_base' build
error on gth2 (and tb0229 also needs this fix.)
board/gth2/libgth2.a(gth2.o): In function `log_serial_char':
/home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base'
common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here
make: *** [u-boot] Error 1
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds changes needed for Makalu rev 1.1:
- Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
- Enable 2nd ethernet port EMAC1
- Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
- Reset PCIe ports via GPIO upon bootup
Signed-off-by: Stefan Roese <sr@denx.de>
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
This patch makes the sequoia board use the generic usb-ohci driver
instead of cpu/ppc4xx/usb_ohci.c.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add cfb console support to FSL 8610 DIU driver.
Inspect board version from PIXIS to obtain correct pixel format.
Use #define CONFIG_VIDEO in config file to enable fb console.
To switch monitor, set monitor variable to
0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS
followed by "diufb init".
Preserve logo bitmap at the top of the fb console.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.
Environmental variable "monitor" is used to specify monitor port.
A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.
diufb init
- initialize the diu driver
Enable the port specified in the environmental variable "monitor"
diufb addr
- display bmp file in memory.
The bmp image should be no bigger than the resolution, 1280x1024
for DVI and double-link LVDS, 1024x768 for single-link LVDS.
Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.
ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Jon loeliger <jdl@freescale.com>
The address in the BAT register is aligned with the BAT size.
The original definition actually did not define BAT for PCIE2 IO.
This patch fix this.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and
"miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which
returns non-zero iff the PHY registers are configured for 1000BASE-X. The
"mii info" command is modified to distinguish between 1000BASE-T and -X.
Signed-off-by: Larry Johnson <lrj@acm.org>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
The configuration file has already enabled USB, but it
missed definition of CFG_OHCI_SWAP_REG_ACCESS, the USB
on MPC8641HPCN can not work because of the wrong USB
register endian.
And add the USB command to U-Boot commands list.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
To get the IDS8247 board working following are done:
- FCC2 is deactivated
- FCC1 is activated
- I2C is activated
- CFI driver is activated
- Adapted for use with LIBFDT
Signed-off-by: Sergej Stepanov <Sergej.Stepanov@ids.de>
--
This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.
Signed-off-by: Stefan Roese <sr@denx.de>
Kumar Gala
Jean-Christophe PLAGNIOL-VILLARD
Vlad Lungu
Wolfgang Denk
Kim Phillips
Jon Loeliger
Roy Zang
Poonam Aggrwal
Jerry Van Baren
Dave Liu
Anton Vorontsov
Nobuhiro Iwamatsu
Yoshihiro Shimoda
John Rigby
Grzegorz Bernacki
Heiko Schocher
Larry Johnson
Guennadi Liakhovetski
Anatolij Gustschin
Matthias Fuchs
Niklaus Giger
Andy Fleming
Timur Tabi
robert lazarski
Joe Hamman
James Yang
Marcel Ziswiler
Rafal Jaworowski
Harald Welte
Stefan Roese
Markus Klotzbücher
David Gibson
Paul Gortmaker
Peter Pearse
Larry Johnson
Martin Krause
Jens Gehrlein
Haavard Skinnemoen
Bartlomiej Sieka
Haiying Wang
Michael Schwingen
Grant Likely
Luotao Fu
Jason Jin
Marian Balakowicz
TsiChungLiew
York Sun
Zhang Wei
Sergej Stepanov