u-boot/arch/powerpc/cpu/mpc8xxx/ddr
Andy Fleming e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
..
Makefile powerpc/8xxx: Add support for interactive DDR programming interface 2011-10-09 17:57:53 -05:00
common_timing_params.h powerpc/8xxx: Enable DDR3 RDIMM support 2010-07-26 13:16:10 -05:00
ctrl_regs.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00
ddr.h powerpc/8xxx: Add support for interactive DDR programming interface 2011-10-09 17:57:53 -05:00
ddr1_dimm_params.c GCC4.6: Squash warnings in ddr[123]_dimm_params.c 2011-10-27 23:54:00 +02:00
ddr2_dimm_params.c GCC4.6: Squash warnings in ddr[123]_dimm_params.c 2011-10-27 23:54:00 +02:00
ddr3_dimm_params.c powerpc/mpc8xxx: Add fine timing support for DDR3 2012-08-23 12:16:55 -05:00
interactive.c powerpc/mpc8xxx: Update DDR registers 2012-10-22 14:31:26 -05:00
lc_common_dimm_params.c arch/powerpc/cpu/mpc8xxx/: sparse fixes 2012-11-04 11:00:36 -07:00
main.c powerpc/mpc8xxx: Fix DDR SPD failed message 2012-10-22 14:31:31 -05:00
options.c powerpc/mpc8xxx: Add auto select bank interleaving mode 2012-10-22 14:31:30 -05:00
util.c 8xxx: Change all 8*xx_DDR addresses to 8xxx 2012-11-27 17:45:17 -06:00