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Fabio Estevam 3b30eece27 mx6sabresd: Make SPL DDR configuration to match the DCD table 
When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.

This causes stability issues like the ones reported at 7dbda25ecd
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .

As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.

The idea is simple: just use the DCD table and write directly to the DDR
registers.

Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)

This method makes it easier for people converting from non-SPL to SPL code.

Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
 		2016-10-04 12:01:14 +02:00
..
Kconfig mx6: remove SYS_SOC from board Kconfig 2015-09-13 10:37:29 +02:00
MAINTAINERS MAINTAINERS/mailmap: Update my email address 2016-01-11 11:22:43 -05:00
Makefile board: arm: convert makefiles to Kbuild style 2013-11-01 11:42:12 -04:00
mx6dlsabresd.cfg mx6dlsabresd: Use its own DCD table 2014-09-09 16:55:22 +02:00
mx6q_4x_mt41j128.cfg imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board 2014-09-22 16:09:56 +02:00
mx6sabresd.c mx6sabresd: Make SPL DDR configuration to match the DCD table 2016-10-04 12:01:14 +02:00