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openblt/Target/Demo/ARMCM4_STM32F4_Olimex_STM32.../Prog/ide/stm32f407.dep

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- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>2</fileVersion>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<fileChecksum>1332848301</fileChecksum>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<configuration>
<name>Debug</name>
<outputs>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<file>$PROJ_DIR$\..\lib\ethernetlib\inc\stm32_eth.h</file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Include\core_cmFunc.h</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<file>$PROJ_DIR$\..\lib\ethernetlib\src\stm32_eth.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Include\core_cm4_simd.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Include\core_cm4.h</file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Include\core_cmInstr.h</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\misc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\misc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_adc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_can.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\stm32f4xx_conf.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_crc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_cryp.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dac.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dbgmcu.h</file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file>$PROJ_DIR$\..\obj\net.lst</file>
<file>$PROJ_DIR$\..\obj\uip.lst</file>
<file>$PROJ_DIR$\..\obj\clock-arch.lst</file>
<file>$PROJ_DIR$\..\obj\stm32_eth.lst</file>
<file>$PROJ_DIR$\..\obj\uip-fw.lst</file>
<file>$PROJ_DIR$\..\obj\uip_timer.lst</file>
<file>$PROJ_DIR$\..\obj\uiplib.lst</file>
<file>$PROJ_DIR$\..\obj\uip_arp.lst</file>
<file>$PROJ_DIR$\..\obj\netdev.lst</file>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<file>$PROJ_DIR$\..\obj\stm32f4xx_can.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_md5.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_sha1.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_crc.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dcmi.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
<file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dac.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dcmi.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dma.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_exti.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_flash.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_aes.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_pwr.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rcc.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_pwr.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_fsmc.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_gpio.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dma.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_i2c.pbi</file>
<file>$PROJ_DIR$\..\obj\boot.o</file>
<file>$PROJ_DIR$\..\obj\main.o</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<file>$PROJ_DIR$\..\bin\demoprog_olimex_stm32e407.out</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<file>$PROJ_DIR$\..\obj\stm32f4xx_i2c.lst</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_sha1.lst</file>
<file>$PROJ_DIR$\..\bin\demoprog_olimex_stm32e407.srec</file>
<file>$PROJ_DIR$\..\obj\demoprog_olimex_stm32e407.map</file>
<file>$PROJ_DIR$\..\obj\led.pbi</file>
<file>$PROJ_DIR$\..\obj\irq.pbi</file>
<file>$PROJ_DIR$\..\obj\system_stm32f4xx.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_aes.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_des.o</file>
<file>$PROJ_DIR$\..\obj\system_stm32f4xx.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_exti.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
<file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
<file>$PROJ_DIR$\..\obj\misc.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dac.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_wwdg.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_adc.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
<file>$PROJ_DIR$\..\obj\misc.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_fsmc.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rtc.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_spi.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_usart.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_tim.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_iwdg.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_sdio.o</file>
<file>$TOOLKIT_DIR$\inc\c\intrinsics.h</file>
<file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_can.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_crc.pbi</file>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<file>$PROJ_DIR$\..\obj\boot.lst</file>
<file>$PROJ_DIR$\..\obj\main.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rtc.pbi</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<file>$PROJ_DIR$\..\obj\stm32_eth.o</file>
<file>$PROJ_DIR$\..\obj\stm32_eth.pbi</file>
<file>$PROJ_DIR$\..\obj\clock-arch.o</file>
<file>$PROJ_DIR$\..\obj\netdev.pbi</file>
<file>$PROJ_DIR$\..\obj\clock-arch.pbi</file>
<file>$PROJ_DIR$\..\obj\netdev.o</file>
<file>$TOOLKIT_DIR$\inc\c\string.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product_string.h</file>
<file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>
<file>$PROJ_DIR$\..\obj\uip-fw.pbi</file>
<file>$PROJ_DIR$\..\obj\uip_arp.o</file>
<file>$PROJ_DIR$\..\obj\uip_timer.o</file>
<file>$PROJ_DIR$\..\obj\uip-fw.o</file>
<file>$PROJ_DIR$\..\obj\uip.pbi</file>
<file>$PROJ_DIR$\..\obj\uip_arp.pbi</file>
<file>$PROJ_DIR$\..\obj\uiplib.o</file>
<file>$PROJ_DIR$\..\obj\uiplib.pbi</file>
<file>$PROJ_DIR$\..\obj\uip_timer.pbi</file>
<file>$PROJ_DIR$\..\obj\uip.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_des.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dbgmcu.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_syscfg.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_wwdg.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rng.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_sdio.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dac.lst</file>
<file>$PROJ_DIR$\..\obj\timer.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_i2c.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_tim.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_iwdg.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_usart.pbi</file>
<file>$TOOLKIT_DIR$\inc\c\cmsis_iar.h</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rng.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_spi.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f407.pbd</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_tim.lst</file>
<file>$PROJ_DIR$\..\obj\led.lst</file>
<file>$TOOLKIT_DIR$\lib\m7M_tl.a</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_spi.lst</file>
<file>$TOOLKIT_DIR$\lib\rt7M_tl.a</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rtc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rng.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rcc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_pwr.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_sdio.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_syscfg.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_usart.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_iwdg.lst</file>
<file>$TOOLKIT_DIR$\lib\dl7M_tln.a</file>
<file>$PROJ_DIR$\..\obj\system_stm32f4xx.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_wwdg.lst</file>
<file>$PROJ_DIR$\..\memory.x</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dma.lst</file>
<file>$PROJ_DIR$\..\obj\irq.lst</file>
<file>$PROJ_DIR$\..\obj\net.o</file>
<file>$PROJ_DIR$\..\obj\net.pbi</file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dcmi.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_dma.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_exti.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_flash.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_fsmc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_gpio.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_hash.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_sha1.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_i2c.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_i2c.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_iwdg.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_iwdg.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_pwr.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rcc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rng.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rng.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rtc.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_sdio.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_spi.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_syscfg.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_tim.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_usart.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_wwdg.h</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Source\system_stm32f4xx.c</file>
<file>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h</file>
<file>$PROJ_DIR$\..\lib\uip\clock-arch.c</file>
<file>$PROJ_DIR$\..\lib\uip\clock-arch.h</file>
<file>$PROJ_DIR$\..\lib\uip\netdev.c</file>
<file>$PROJ_DIR$\..\lib\uip\netdev.h</file>
<file>$PROJ_DIR$\..\lib\uip\uip-conf.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\clock.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip-fw.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip-fw.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_arch.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_arp.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_arp.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_timer.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_timer.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uiplib.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uiplib.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uipopt.h</file>
<file>$PROJ_DIR$\..\boot.c</file>
<file>$PROJ_DIR$\..\boot.h</file>
<file>$PROJ_DIR$\..\cstart.s</file>
<file>$PROJ_DIR$\..\header.h</file>
<file>$PROJ_DIR$\..\led.c</file>
<file>$PROJ_DIR$\..\led.h</file>
<file>$PROJ_DIR$\..\main.c</file>
<file>$PROJ_DIR$\..\net.c</file>
<file>$PROJ_DIR$\..\net.h</file>
<file>$PROJ_DIR$\..\timer.c</file>
<file>$PROJ_DIR$\..\timer.h</file>
<file>$PROJ_DIR$\..\vectors.c</file>
<file>$PROJ_DIR$\..\irq.h</file>
<file>$PROJ_DIR$\..\irq.c</file>
<file>$PROJ_DIR$\..\obj\led.o</file>
<file>$PROJ_DIR$\..\obj\cstart.o</file>
<file>$PROJ_DIR$\..\obj\timer.o</file>
<file>$PROJ_DIR$\..\obj\boot.pbi</file>
<file>$PROJ_DIR$\..\obj\vectors.o</file>
<file>$PROJ_DIR$\..\obj\vectors.lst</file>
<file>$PROJ_DIR$\..\..\Boot\blt_conf.h</file>
<file>$PROJ_DIR$\..\obj\irq.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_flash.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_rcc.o</file>
<file>$PROJ_DIR$\..\obj\main.pbi</file>
<file>$PROJ_DIR$\..\obj\vectors.pbi</file>
<file>$PROJ_DIR$\..\obj\timer.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_md5.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_gpio.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_md5.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_aes.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_can.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_des.lst</file>
<file>$TOOLKIT_DIR$\lib\shb_l.a</file>
<file>$PROJ_DIR$\..\obj\misc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_syscfg.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_hash_sha1.pbi</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_adc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_exti.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dbgmcu.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_crc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dcmi.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_flash.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_fsmc.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_gpio.lst</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_adc.o</file>
<file>$PROJ_DIR$\..\obj\stm32f4xx_dbgmcu.o</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</outputs>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\ethernetlib\src\stm32_eth.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 28 95</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 96</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 0 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 0 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\misc.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 249 79</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 74</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</outputs>
<inputs>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<tool>
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 7 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 7 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 254 262</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 77</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 10 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 246 34</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 90</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</outputs>
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 12 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 12 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 257 38</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 91</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 15 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 15 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 252 35</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 122</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 245 67</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 47</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 247 68</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 114</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 253 70</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 85</file>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 17 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 120 42</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 75</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 22 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 22 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
</tool>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
</inputs>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 256 263</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 115</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 24 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 24 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>[ROOT_NODE]</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ILINK</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 58 62</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</outputs>
</file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file>
<name>$PROJ_DIR$\..\bin\demoprog_olimex_stm32e407.out</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 62</file>
</tool>
<tool>
<name>OBJCOPY</name>
<file> 61</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 149 56 97 229 228 57 79 152 100 95 262 34 38 35 67 68 70 42 263 43 44 45 46 51 52 53 36 37 123 127 48 237 118 81 87 82 116 84 83 76 69 230 107 113 105 106 110 232 248 137 135 146</file>
</tool>
</inputs>
</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<file>
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c</name>
<outputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 258 43</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 39</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</outputs>
<inputs>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<tool>
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 155 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 155 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 150 44</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 54</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 157 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 157 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c</name>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<outputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 255 45</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 71</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 159 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 159 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
</inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 259 46</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 236</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 161 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 161 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 260 51</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 80</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 163 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 163 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 261 52</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 242</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 165 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 165 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- Use system reset to reactivate the bootloader from the demo user programs for Cortex Mx. - Use cs-make/cs-rm in GCC demos. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@70 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-02-06 14:37:04 +00:00
</inputs>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash.c</name>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
<outputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 124 53</file>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 243</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 241 36</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 244</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_sha1.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 60 37</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 251</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 167 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_i2c.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 59 123</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 55</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 171 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 171 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
</inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_iwdg.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 145 127</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 86</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 173 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 175 177 179 181 183 185 187 189 191 193 7</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 173 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 141 48</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 50</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</outputs>
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 175 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 177 179 181 183 185 187 189 191 193 7</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 175 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 177 179 181 183 185 187 189 191 193 7</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 140 237</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 49</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 177 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 177 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rng.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 139 118</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 130</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 179 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 179 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 138 81</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 94</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</outputs>
<inputs>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 181 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 181 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 183 185 187 189 191 193 7</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 142 87</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 119</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 183 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 183 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 136 82</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 131</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 185 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 185 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 143 116</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 250</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 187 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 187 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 133 84</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 125</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 189 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 191 193 7</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 189 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 144 83</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 128</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 191 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 191 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 148 76</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 117</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 193 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 193 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Source\system_stm32f4xx.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 147 69</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 65</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\uip\clock-arch.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 27 97</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 99</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 197 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 197 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\lib\uip\netdev.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 33 100</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 98</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 208 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 219 224 0 101 103 102</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 208 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 219 224 0 101 103 102</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip-fw.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 29 107</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 104</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 205 203 101 73 40 78 66 72 41 126 103 102</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 205 203 101 73 40 78 66 72 41 126 103 102</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 26 113</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 108</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 205 101 73 40 78 66 72 41 126 103 102</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 205 101 73 40 78 66 72 41 126 103 102</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_arp.c</name>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 32 105</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 109</file>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
</tool>
</outputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 208 206 213 200 215 222 101 73 40 78 66 72 41 126 103 102</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 208 206 213 200 215 222 101 73 40 78 66 72 41 126 103 102</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
- Added support for automatically generating the source code documentation with Doxygen. - Converted all comments to the Doxygen format. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@53 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-07-31 15:48:23 +00:00
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uip_timer.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 30 106</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 112</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 201 197 210</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 201 197 210</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip\uiplib.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 31 110</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 111</file>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- added support for CAN1 and CAN2 on the STM32CM4 target. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@57 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-08-15 14:20:46 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 212</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 206 213 200 215 222 212</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\boot.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 92 56</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 231</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>$PROJ_DIR$\..\cstart.s</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>AARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 229</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</outputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\led.c</name>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<outputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 134 228</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 63</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</outputs>
<inputs>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
<tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
</tool>
<tool>
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\main.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 93 57</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 238</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</outputs>
<inputs>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- It is now possible to have more than 1 communication interface configured. - Fixed a bug where certain UART drivers did not work anymore when building with #define NDEBUG. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@89 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-05-26 23:14:30 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\net.c</name>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 25 152</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 153</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</outputs>
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222 199 206 213 200 208</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222 199 206 213 200 208</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\timer.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 240 230</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 121</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</outputs>
<inputs>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- Moved redundant non-controller specific headers to a central place in the bootloader core. Refs #52. - Set version to 1.2.0. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@129 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-02-25 13:51:12 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\vectors.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 233 232</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 239</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</outputs>
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 219 224 222</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</inputs>
</file>
<file>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<name>$PROJ_DIR$\..\irq.c</name>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
<outputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 151 235</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 64</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
</outputs>
<inputs>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>ICCARM</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 226 219 224 222</file>
- added TCP/IP networking support to the STM32-E407 demo bootloader. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@96 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 09:26:57 +00:00
</tool>
<tool>
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
<name>BICOMP</name>
Refs #145. Refactoring: ARMCM4_STM32 renamed to ARMCM4_STM32F4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@168 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-24 09:42:30 +00:00
<file> 217 234 8 4 89 73 40 78 66 72 41 126 5 129 88 1 3 195 13 10 12 15 17 22 24 155 157 159 161 163 167 165 171 173 175 177 179 181 183 185 187 189 191 193 7 215 226 219 224 222</file>
- Added support for Cortex CM4 for STM32/IAR - Added a demo for the Olimex STM32-E407 board with UART/SD-card git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@45 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-05-28 21:43:27 +00:00
</tool>
</inputs>
</file>
</configuration>
<configuration>
<name>Release</name>
<outputs/>
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
<forcedrebuild>
<name>[REBUILD_ALL]</name>
</forcedrebuild>
</configuration>
</project>