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Added Freescale HCS12 port including a Dragon12plus demo. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@60 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-09-18 10:39:57 +00:00
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- Fixed bug where main() was incorrectly called in Startup() for HCS12 targets. - Added support for BDM debugging of the demo program for HCS12 targets. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@63 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-10-09 09:17:10 +00:00
S2240FC000FEC03DFDC03B270E35ED31EC3169700434FB310326F2FEC03FEC31270BED31189A
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
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- modified all demo programs so that bootloader activation is done by a software reset instead of just calling the bootloader's reset vector. - refactored some code to make it easier to adjust the size of the bootloader. - improved informative text for certain Microboot interface dll's git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@97 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 14:53:07 +00:00
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S2240FC1E03D1B9C1F014401641E01610810FC016049494949496C82C7876C80202EFE016235
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
S2240FC200FC0160C4078749B7C54656CD00003BFC0160C4E03BC60334EE8216C326EA85AA31
- modified all demo programs so that bootloader activation is done by a software reset instead of just calling the bootloader's reset vector. - refactored some code to make it easier to adjust the size of the bootloader. - improved informative text for certain Microboot interface dll's git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@97 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2014-07-22 14:53:07 +00:00
S2240FC220846C88B754EA81AA806CA5EC828C06672616EC802612F6016404A10CF6016526EC
Refs #81. - Refactored the CPU module for all targets. - Added automatic interrupt enabling for ARM Cortex M3/M4. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@156 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2016-10-17 23:08:45 +00:00
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Added Freescale HCS12 port including a Dragon12plus demo. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@60 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
2013-09-18 10:39:57 +00:00
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